Browsing by Author "Lu, Guo-Quan"
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- Adhesion Strength of Cordierite Bulk Coatings on Molybdenum SubstratesKuhr, Thomas A. (Virginia Tech, 1997-07-23)Cordierite was adhered to molybdenum using various metallic interlayers of copper, nickel, and chromium. The development of a coating adhesion test methodology was required to choose between interface designs. An indentation method was chosen because of ease in testing and availability of fracture mechanics interpretations of test data. The interfacial fracture toughness was determined from indentation load vs. crack length data by examining the residual stress and critical buckling load of the ceramic coatings. The interfacial fracture toughness values obtained using a slightly different indentation analysis agree with those in the literature. Quantitative chemical analysis of the interface microstructure was used to explain differences in interfacial fracture toughness values for samples with different metallic interlayer designs. The best interface design for adhering cordierite glass-ceramic coatings to molybdenum was found to be molybdenum / 2 μm copper / 4 μm chromium / cordierite.
- Advanced Control Schemes for Voltage RegulatorsLee, Kisun (Virginia Tech, 2008-03-28)The microprocessor faces a big challenge of heat dissipation. In order to enhance the performance of the microprocessor without increasing the heat dissipation, the leading microprocessor company, Intel, uses several methods to reduce the power consumption. Theses methods include enhanced sleep states control, the Speed Step technology, and multi-core architecture. These are closely related to the Voltage Regulator (VR), a dedicated power supply for the microprocessor and its control method. The speed of the VR control system should be high in order to meet the stringent load-line requirements with the high current and high di/dt, otherwise, a lot of decoupling capacitors are necessary. Capacitors make the VR cost and size higher. Therefore, the VR control method is very important. This dissertation discusses the way to increase the speed of VR without degrading other functions, such as the system efficiency, and the required control functions (AVP, current sharing and interleaving). The easiest way to increase the speed of the VR is to increase the switching frequency. However, higher switching frequency results in system efficiency degradation. This paper uses two approaches to deal with this issue. The first one is the architecture approach. The other is the fast transient control approach. For the architecture approach, a two-stage architecture is chosen. It is already shown that with a two-stage architecture, the switching frequency of the second stage can be increased, while keeping the same system efficiency. Therefore with the two-stage architecture, a high performance VR can be easily implemented. However, the light-load efficiency of two-stage architecture is not good because the bus voltage is designed for the full-load efficiency which is not optimized for the light load. The light-load efficiency is also important factor and it should be maximized because it is related to the battery life of mobile application or the energy utilization. Therefore, Adaptive Bus Voltage Positioning (ABVP) control has been proposed. By adaptively adjusting the bus voltage according to the load current, the system efficiency can be optimized for whole load range. The bus voltage rate of change is determined by the first stage bandwidth. In order to maintain regulation during a fast dynamic load, the first stage bandwidth should be high. However, it is observed from hardware when the first stage bandwidth is higher, the ABVP system can become unstable. To get a stable system, the first stage bandwidth is often designed to be slow which causes poor ABVP dynamic response. The large number of bus capacitors necessary for this also increases the size and cost. In this dissertation, in order to raise the first stage bandwidth, a stability analysis is performed. The instability loop (TABVP) is identified, and a small signal model to predict this loop is suggested. TABVP is related to the first stage bandwidth. With the higher first stage bandwidth, the peak magnitude of TABVP is larger. When the peak magnitude of TABVP touches 0dB, the system becomes unstable. Two solutions are proposed to reduce this TABVP magnitude without decreasing the first stage bandwidth. One method is to increase the feedforward gain and the other approach is to use a low pass filter. With these strategies, the ABVP system can be designed to be stable while pushing first stage bandwidth as high as possible. The ABVP-AVP system and its design are verified with hardware. For the fast transient control approach hysteretic control is chosen because of its fast transient and high light-load efficiency with DCM operation. However, in order to use the hysteretic control method for multiphase VR applications interleaving must be implemented. In this dissertation, a multiphase hysteretic control method is proposed which can achieve interleaving without losing its benefits. Using the phase locked loop (PLL), this control method locks the phase and frequency of the duty cycles to the reference clocks by modifying the size of the hysteretic band, to say, hysteretic band width. By phase shifting the reference clocks, interleaving can be achieved under steady state. During the load transient, the system loses the phase-locking function due to the slow hysteretic band width changing loop, and the system then reacts quickly to the load change without the interruption from the phase locking function (or the interleaving function). The proposed hysteretic control method consists of two loops, the fast hysteretic control loop and the slow hysteretic band width changing loop. These two nonlinear loops are difficult to model and analyze together. Therefore, assuming these two loops can be separated because of the speed difference, the phase plane model is used for the fast hysteretic control loop and the sampled data model is then used for the slow hysteretic band width changing loop. With these models, the proposed hysteretic control method can be analyzed and properly designed. However, if the transient occurs before the slow hysteretic band width changing loop settles down, the transient may start with the large hysteretic band width and the output voltage peak can exceed the specification. To prevent this, a hysteretic band width limiter is inserted. With the hardware, the proposed hysteretic control method and its design are verified. A two-phase VR with 300kHz switching frequency is built and the output capacitance required is only 860μF comparing to 1600μF output capacitance with the 50kHz bandwidth linear control method. That is about 46% capacitor reduction. The proposed hysteretic control method saturates the controller during the transient and the transient peak voltage is determined by the power stage parameters, the inductance and the output capacitors. By decreasing the inductance, the output capacitors are reduced. However, small inductance results in the low efficiency. In order to resolve this, the coupled inductor is used. With the coupled inductor, the transient inductance can be reduced with the same steady state inductance. Therefore, the transient speed can be faster without lowering down the system efficiency. The proposed hysteretic control method with the coupled inductor can be implemented using the DCR current sensing network. A two-phase VR with the proposed hysteretic control and the coupled inductor is built and the output capacitance is only 660μF comparing to 860μF output capacitance with the proposed hysteretic control only. A 23% capacitor reduction is achieved. And compared to the 50kHz bandwidth linear control method, a 60% capacitor reduction is achieved.
- Advanced Integrated Single-Stage Power Factor Correction TechniquesZhang, Jindong (Virginia Tech, 2001-03-15)This dissertation presents the in-depth study and innovative solutions of the advanced integrated single-stage power-factor-correction (S2PFC) techniques, which target at the low- to medium-level power supplies, for wide range of applications, from power adapters and computers to various communication equipment. To limit the undesirable power converter input-current-harmonic's impact on the power line and other electronics equipment, stringent current harmonic regulations such as IEC 61000-3-2 have already been enforced. The S2PFC techniques have been proposed and intensively studied, in order to comply these regulations with minimal additional component count and cost. This dissertation provides a systematic study of the S2PFC input-current-shaping (ICS) mechanism, circuit topology generalization and variation, bulk capacitor voltage stress and switch current stress, converter design and optimization, and evaluation of the state-of-the-art S2PFC techniques with universal-line input. Besides, this presentation also presents the development of novel S2PFC techniques with a voltage-doubler-rectifier front end to both improve the performance and reduce the cost of S2PFC converters for (international voltage range) universal-line applications. The calculation and experimental results show that the proposed techniques offer a more cost-effective and efficient solution than industries' current practice, with universal-line input and converter power level up to 600 W. Finally, further improved technique is also presented with reduced filter inductor size and increased power density.
- Advanced Semiconductor Device and Topology for High Power Current Source ConverterXu, Zhenxue (Virginia Tech, 2003-12-02)This dissertation presents the analysis and development of an innovative semiconductor device and topology for the high power current source converter (CSC). The CSC is very attractive in high power applications due to its lower output dv/dt, easy regeneration capability and implicit short-circuit protection. Traditionally, either a symmetrical gate turn-off (GTO) thyritor or an asymmetrical GTO in series with a diode is used as the power switch in the CSC. Since the GTO has a lower switching speed and requires a complicated gate driver, the symmetrical GTO based CSC usually has low dynamic response speed and low efficiency. To achieve high power rating, fast dynamic response speed and low harmonics, an advanced semiconductor device and topology are needed for the CSC. Based on symmetrical GTO and power MOSFET technologies, a symmetrical emitter turn-off (ETO) thyristor is developed that shows superior switching performance, high power rating and reverse voltage blocking capability. The on-state characteristics, forced turn-on characteristics, forced turn-off characteristics and the load-commutated characteristics are studied. Test results show that although the load-commutation loss is high, the developed symmetrical ETO is suitable for use in high power CSC due to its low conduction loss, fast switching speed and reverse voltage blocking capability. The snubberless turn-on capability is preferred for a semiconductor device in a power conversion system, and can be achieved for devices with forward biased safe operation area (FBSOA). The FBSOA of the ETO is investigated and experimentally demonstrated. The ETO device has excellent FBSOA due to the negative feedback provided by the emitter switch. However, the FBSOA for a large area ETO is poor. A new ETO concept is therefore proposed for future development in order to demonstrate the FBSOA over a large area device. To improve the turn-on performance of the large area ETO, a novel concept, named the transistor-mode turn-on, is proposed and studied. During the transistor-mode turn-on process, the ETO behaves like a transistor instead of a thyristor. Without a snubber, the transistor-mode turn-on for the ETO is hard to achieve. Through the selection of a proper gate drive and di/dt snubber, the transistor-mode turn-on can be implemented, and the turn-on performance for the ETO can be dramatically improved. To increase the power rating of the CSC without degrading the utilization of power semiconductor devices, a novel multilevel CSC, named the parallel-cell multilevel CSC, is proposed. Based on a six-switch CSC cell, the parallel-cell multilevel CSC has the advantages of high power rating, low harmonics, fast dynamic response and modularity. Therefore, it is very suitable for high power applications. The power stage design, modeling, control and switching modulation scheme for a parallel-cell multilevel CSC based static var compensator (STATCOM) are analyzed and verified through simulation.
- Alternative structures for integrated electromagnetic passivesLiu, Wenduo (Virginia Tech, 2006-04-19)The demand for high power density keeps driving the development of electromagnetic integration technologies in the field of power electronics. Based on planar homogeneous integrated structures, the mechanism of the electromagnetic integration of passives has been investigated with distributed-parameter models. High order modeling of integrated passives has been developed to investigate the electromagnetic performance. The design algorithm combining electromagnetic design and loss models has been developed to optimize and evaluate the spiral winding structure. High power density of 480 W/in3 has been obtained on the prototype. Due to the structural limitation, the currently applied planar spiral winding structure does not sufficiently utilize the space, and the structure is mechanically vulnerable. The improvement on structures is necessary for further application of integrated passives. The goal of this research is to investigate and evaluate alternative structures for high-power-density integrated passives. The research covers electromagnetic modeling, constructional study, design algorithm, loss modeling, thermal management and implementation technology The symmetric single layer structure and the stacked structure are proposed to overcome the disadvantages of the currently applied planar spiral winding structure. Because of the potential of high power density and low power loss, the stacked structure is selected for further research. The structural characteristics and the processing technologies are addressed. By taking an integrated LLCT module as the study case, the general design algorithm is developed to find out a set of feasible designs. The obtained design maps are used to evaluate the constraints from spatial, materials and processing technologies for the stacked structure. Based on the assumption of one-dimensional magnetic filed on the cross-section and linear current distribution along the longitudinal direction of the stacked structure, the electromagnetic field distribution is analyzed and the loss modeling is made. The experimental method is proposed to measure the loss and to verify the calculation. The power loss in the module leads to thermal issues, which limit the processed power of power electronics modules and thus limit the power density. To further improve the power handling ability of the module, the thermal management is made based on loss estimation. The heat extraction technology is developed to improve the heat removal ability and further improve the power density of integrated passives. The experimental results verify the power density improvement from the proposed stacked structure and the applied heat extraction technology. The power density of 1147 W/in3 (70 W/cm3) is achieved in the implemented LLCT module with the efficiency of 97.8% at output power of 1008W.
- Carrier transport properties measurements in wide bandgap materialsCropper, André D. (Virginia Tech, 1995-04-07)This dissertation examines the carrier transport properties, diffusion length, effective carrier lifetime, and resistivity in two wide bandgap materials, GaN and diamond. A combination of two methods was used to obtain these transport properties. The two were optical beam induced current (OBIC) and electron beam induced current (EBIC) time of flight transient measurements. These techniques consist of measuring the current response to the drift and diffusion of generated electron-hole pair carriers created by a short-duration pulse of radiation. Under OBIC, a short duration pulsed optical source, with an electron beam excitation pulse time much less than the transit time of the material, was used to generate excess carriers within the absorption depth of the material. The second method of excitation, EBIC involved the use of a modified SEM with a photoemission source (L-EBIC) and a high speed pulsed thermionic electron source (T-EBIC) to generate an electron beam. This electron beam was used to create a large number of electron-hole pairs at various penetration depths within the materials. Measurements on GaN found the diffusion length was 7.84 µm with the L-EBIC and 7.78 µm with the T-EBIC. After annealing at 900°C for 30 min. the GaN diffusion length increased to 9.89 µm (L-EBIC). The dark resistivity was 1.79 x 10¹⁰Ω-cm, and the carrier lifetimes were 1.7 µs with L-EBIC and 3.36 & 3.9 ns with OBIC. The author believed that the L-EBIC result was a good representation of the carrier lifetime within the material, while the shorter OBIC results were due to the combine high surface and interface recombination processes. The diamond dark resistivity was found to be 6.14 x 10¹¹Ω-cm and the diffusion lengths were 94.1 µm and 97 µm from the L-EBIC and T-EBIC respectively. All measurements were within 10 % spread. The real value of this contribution lies in determining the diffusion lengths in GaN and diamond by the EBIC techniques, measuring the effective surface\interface and thin film carrier lifetime of GaN utilizing a combination of OBIC and L-EBIC techniques, and evaluating the dark resistivity in GaN and diamond materials. These measurements can lead to a better understanding and exploitation of the electrophysical behavior of these materials.
- Characterization and modeling of silicon and silicon carbide power devicesYang, Nanying (Virginia Tech, 2010-11-05)Power devices play key roles in the power electronics applications. In order for the power electronics designers to fully utilize the performance advantages of power devices, compact power device models are needed in the circuit simulator (Saber, P-spice, etc.). Therefore, it is very important to get accurate device models. However, there are many challenges due to the development of new power devices with new internal structure and new semiconductor materials (SiC, GaN, etc.). In this dissertation, enhanced power diode model is presented with an improvement in the reverse blocking region. In the current power diode model in the Saber circuit simulator, an empirical approach was used to describe the low-bias reverse blocking region by introducing an effect called "conduction loss," a parameter that causes a linear relationship between the device voltage and current at low bias voltages with no physics meaning. Furthermore, this term is not sufficient to accurately describe the changes to the device characteristics as the junction temperature is varied. In the enhanced model, an analytical temperature dependent model for the reverse blocking characteristics has been developed for Schottky/JBS diodes by including the thermionic-emission mechanism in the low-bias range. The newly derived model equations have been implemented in Saber circuit simulator using MAST language. An automated parameter extraction software package developed for constructing silicon (Si) and silicon carbide (SiC) power diode models, which is called DIode Model Parameter extrACtion Tools (DIMPACT). This software tool extracts the data necessary to establish a library of power diode component models and provides a method for quantitatively comparing between different types of devices and establishing performance metrics for device development. This dissertation also presents a new Saber-compatible approach for modeling the inter-electrode capacitances of the Si CoolMOSTM transistor. This new approach accurately describes all three inter-electrode capacitances (i.e., gate-drain, gate-source, and drain-source capacitances) for the full operating range of the device. The model is derived using the actual charge distribution within the device rather than assuming a lumped charge or one-dimensional charge distribution. The comparison between the simulated data with the measured results validates the accuracy of the new physical model.
- Characterization, Reliability and Packaging for 300 °C MOSFETNam, David (Virginia Tech, 2020-03-06)Silicon carbide (SiC) is a wide bandgap material capable of higher voltage and higher temperature operation compared to its silicon (Si) counterparts due to its higher critical electric field (E-field) and higher thermal conductivity. Using SiC, MOSFETs with a theoretical high temperature operation and reliability is achievable. However, current bottlenecks in high temperature SiC MOSFETs lie within the limitations of standard packaging. Additionally, there are reliability issues relating to the gate oxide region of the MOSFET, which is exacerbated through high temperature conditions. In this thesis, high temperature effects on current-generation SiC MOSFETs are studied and analyzed. To achieve this, a high temperature package is created to achieve reliable operation of a SiC MOSFET at junction temperatures of 300 °C. The custom, high temperature package feasibility is verified through studying trends in SiC MOSFET behavior with increasing temperature up to 300 °C by static characterization. Additionally, the reliability of SiC MOSFETs at 300 °C is tested with accelerated lifetime bias tests.
- Characterizations of Rapid Sintered Nanosilver Joint for Attaching Power ChipsFeng, Shuang-Tao; Mei, Yunhui; Chen, Gang; Li, Xin; Lu, Guo-Quan (MDPI, 2016-07-12)Sintering of nanosilver paste has been extensively studied as a lead-free die-attach solution for bonding semiconductor power chips, such as the power insulated gated bipolar transistor (IGBT). However, for the traditional method of bonding IGBT chips, an external pressure of a few MPa is reported necessary for the sintering time of ~1 h. In order to shorten the processing duration time, we developed a rapid way to sinter nanosilver paste for bonding IGBT chips in less than 5 min using pulsed current. In this way, we firstly dried as-printed paste at about 100 °C to get rid of many volatile solvents because they may result in defects or voids during the out-gassing from the paste. Then, the pre-dried paste was further heated by pulse current ranging from 1.2 kA to 2.4 kA for several seconds. The whole procedure was less than 3 min and did not require any gas protection. We could obtain robust sintered joint with shear strength of 30–35 MPa for bonding 1200-V, 25-A IGBT and superior thermal properties. Static and dynamic electrical performance of the as-bonded IGBT assemblies was also characterized to verify the feasibility of this rapid sintering method. The results indicate that the electrical performance is comparable or even partially better than that of commercial IGBT modules. The microstructure evolution of the rapid sintered joints was also studied by scanning electron microscopy (SEM). This work may benefit the wide usage of nanosilver paste for rapid bonding IGBT chips in the future.
- Characterizing the Effects of Mechanical Alloying on Solid State Amorphization of Nanoscaled Multilayered Ni-TiMonsegue, Niven (Virginia Tech, 2010-07-09)Equiatomic composition of Ni and Ti was cryomilled with varying milling times to create Ni-Ti lamella structures with average spacings of 50 nm, 470 nm, and 583 nm in powder particles to vary the interfacial surface area per volume. These surfaces form interfaces for diffusion that are essential for solid state amorphization during low temperature annealing. To compare solid state amorphization in a relatively defect free multilayer system, elemental Ni and Ti were deposited by electron beam physical vapor deposition on titanium plates with comparable spacing as above. Both milled and deposited multilayers were annealed between 225 and 350°C for up to 50 hours. X-ray diffraction characterization and in situ annealing was conducted on cryomilled and deposited multilayers of Ni-Ti. Based on this characterization, an amorphization model based on the Johnson-Mehl-Avrami nucleation and growth equation has been established to predict the amorphization of both cryomilled and deposited multilayers. Cryomilled powders experienced much larger amorphization rates during annealing than that of deposited multilayer structures, for all layer spacings. This superior amorphization is seen despite the formation of amorphous phase during the milling process; the amount of which increases with increasing milling time. The difference in amorphization rates between cryomilled and deposited multilayers is attributed to excess driving force due to the extensive preexisting defects in the powders caused by cryomilling. Serial 3D reconstruction of cryomilled Ni-Ti powders was done by scanning electron microscopy and focused ion beam. Through 3D reconstruction it was observed that a random and non-linear lamella structure has been formed in cryomilled powders. Furthermore, lamellar spacing was seen to become smaller with increased milling time while at the same time becoming more homogeneous through the material's volume. 3D reconstruction of cryomilled Ni-Ti offers a unique insight into the microstructures and surface areas of cryomilled powder particles that has never been accomplished.
- Chemical vapor deposition of β-SiC thin films on Si(100) in a hot wall reactorChiu, Chienchia (Virginia Tech, 1994-01-12)A systematic method was developed for the deposition of β-SiC thin films on Si(100) substrates in a hot wall reactor, using low pressure chemical vapor deposition (LPCVD). Due to poor adhesion resulting from lattice mismatch and difference in thermal expansion coefficients between the (SiC films and the Si(100) substrates, the feasibility of forming a SiC buffer layer on the Si(100) surface before beginning the chemical vapor deposition (CVD) process was investigated. The SiC buffer layers were formed with either a smooth or porous morphology. A nonporous Si(100) substrate with a 35Å thick SiC buffer layer was formed when the Si surface was heated at 1050°C in an atmosphere of C₂H₂ and H₂. A porous surface was obtained when the Si substrate was heated at 1000°C in C₂H₂ alone. The porous defects were correlated to the out—diffusion of Si in the carburizing process. On smooth Si(100) substrates, polycrystalline and stoichiometric β-SiC thin films with the (111) planes paralleling the Si(100) substrates were grown from a CH₃SiCl₃ (MTS)—H₂ mixture at 1050°C. At high H₂/MTS ratios and/or low deposition pressures, no etching on the Si substrates of the β-SiC films was observed, resulting in a smooth topography. Degradation in film morphology, changes in the preferred orientation, and etching of the Si substrates were observed at higher pressures, temperatures, and H₂/MTS ratios. The etching of the Si substrate was due to the out—diffusion of Si atoms from the substrate and the presence of Cl—containing radicals, which resulted from the decomposition of MTS molecules before arriving at the substrates. A model of the deposition mechanism is proposed which predicts the deposition rates in a hot wall CVD reactor and agrees very well with the experimental data. On the Si(100) substrate with a porous topography, epitaxial β-SiC(100) thin films were grown from MTS—H₂ at 1150°C. The crystallinity of the deposited films was influenced by the deposition time. With increasing deposition time, rotational β-SiC(100) crystals and polycrystalline β-SiC with a highly preferred orientation of (100) and/or (111) were obtained. At a lower temperature of 1100°C, poor morphology and polycrystalline β-SiC thin films were observed. Finally, a new approach to the calculation of the local equilibrium CVD phase diagrams, which represent the most stable phases above the substrates in a hot wall reactor, for SiC deposition from the MTS—H₂ gas mixture by coupling the depletion effects to the equilibrium thermodynamic computer code SOLGASMIX—PV. The calculated CVD phase diagrams were also compared with experimental and the literature data. Although the local equilibrium CVD phase diagrams predicted the deposition of single phase SiC better than established CVD phase diagrams, the experimental regions for depositing single phase SiC are larger than those calculated from local CVD phase diagrams. This may be because of the high linear velocity of the gas flux under low pressure and the polarity of the Si—containing intermediate species.
- Code Division Multiplexing of Fiber Optic and Microelectromechanical Systems (MEMS) SensorsJacobson, Carl P. (Virginia Tech, 2000-02-22)Multiplexing has evolved over the years from Emile Baudot's method of transmitting six simultaneous telegraph signals over one wire to the high-speed mixed-signal communications systems that are now commonplace. The evolution started with multiplexing identical information sources, such as plain old telephone service (POTS) devices. Recently, however, methods to combine signals from different information sources, such as telephone and video signals for example, have required new approaches to the development of software and hardware, and fundamental changes in the way we envision the basic block diagrams of communication systems. The importance of multiplexing cannot be overstated. To say that much of the current economic and technological progress worldwide is due in part to mixed-signal communications systems would not be incorrect. Along the vein of advancing the state-of-the-art, this dissertation research addresses a new area of multiplexing by taking a novel approach to network different-type sensors using software and signal processing. Two different sensor types were selected, fiber optics and MEMS, and were networked using code division multiplexing. The experimentation showed that the interconnection of these sensors using code division multiplexing was feasible and that the mixed signal demultiplexing software unique to this research allowed the disparate signals to be discerned. An analysis of an expanded system was performed with the results showing that the ultimate number of sensors that could be multiplexed with this technique ranges from the hundreds into the millions, depending on the specific design parameters used. Predictions about next-next generation systems using the techniques developed in the research are presented.
- Computer Aided Design and Fabrication of Magnetic Composite Multilayer InductorsFielder, Robert Stanley (Virginia Tech, 2000-12-04)Computer modeling using finite element analysis (FEA) was performed to examine the effects of constructing multilayered thick film inductors using an artificially modulated magnetic composite structure. It was found that selectively introducing regions of low permeability material increased both the inductance and the current carrying capacity compared to thick film inductors made with single material magnetic cores. Permeabilities of the composite cores ranged from 1 to 220. The frequency for the models ranged from 0 to 5.0 MHz. Experimental devices were constructed using thick film screen printing techniques and characterized to validate the models and to determine the effectiveness of the design modifications. Quantitative comparisons were made between inductors of single permeability cores with inductors produced with magnetic composite cores. It was found that significant (> 130%) increases could be gained in saturation current with only a 12% decrease in inductance. It was found that the key parameters affecting performance were 1) the placement of low permeability regions, 2) the extent of non-uniform flux distribution within the structure, and 3) the volume fraction of low permeability material.
- Constrained sintering of gold circuit films on rigid substratesChoe, JoonWon (Virginia Tech, 1994-07-15)The densification behavior of porous gold films made from commercial circuit paste used in microelectronic packaging applications was studied. Constrained gold circuit films of 60-65μm thick were formed by multiple screen printing of the gold paste on rigid alumina substrates, while freestanding films were obtained by carefully peeling off gold films from the substrates after binder burn-out. Optical techniques were developed to determine the densification kinetics of the constrained and freestanding films at temperatures below 1000°C. The densification kinetics of gold films constrained on rigid substrates were observed to be significantly retarded relative to the free films, at all sintering temperatures between 650°C and 900°C studied. SEM studies revealed the microstructure of the constrained films to be much more porous than its freestanding film counterpart. Considerably higher sintering temperatures were required to obtain densities comparable to those of freestanding films. SEM studies also showed no significant difference in grain size between the sintered freestanding and constrained gold films. Inplane tensile stresses generated during constrained-film sintering, was determined to have a maximum value of 460 KPa at the sintering temperature of 750°C. The negligible difference in grain size between the sintered freestanding and constrained gold films, and the small magnitude of the measured tensile stresses, were both determined to be insufficient to account for the observed retardation in the densification kinetics of the constrained gold films. The activation energies for densification of the porous gold films during isothermal sintering, were found to be 21.54±1.03 Kcal/mole and 45.12±1.6 Kcal/mole for freestanding and constrained gold films respectively. These values corresponded very well with the activation energies for grain-boundary diffusion and lattice diffusion respectively, for gold as found in literature. Hence from our results of the activation energies for densification of the constrained and freestanding gold films, coupled with our studies on grain growth and stress, we suggest that the observed retardation in the densification kinetics of the constrained gold films are due to a change in the dominant diffusion mechanism during sintering of the porous gold films constrained on rigid substrates.
- Crystallization of Lithium Disilicate Glass Using Variable Frequency Microwave ProcessingMahmoud, Morsi Mohamed (Virginia Tech, 2007-04-24)The lithium disilicate (LS2) glass system provides the basis for a large number of useful glass-ceramic products. Microwave processing of materials such as glass-ceramics offers unique benefits over conventional processing techniques. Variable frequency microwave (VFM) processing is an advanced processing technique developed to overcome the hot spot and the arcing problems in microwave processing. In general, two main questions are addressed in this dissertation: 1. How does microwave energy couple with a ceramic material to create heat? and, 2. Is there a "microwave effect" and if so what are the possible explanations for the existence of that effect? The results of the present study show that VFM processing was successfully used to crystallize LS2 glass at a frequency other than 2.45 GHz and without the aid of other forms of energy (hybrid heating). Crystallization of LS2 glass using VFM heating occurred in a significantly shorter time and at a lower temperature as compared to conventional heating. Furthermore, the crystallization mechanism of LS2 glass in VFM heating was not exactly the same as in conventional heating. Although LS2 crystal phase (Orthorhombic Ccc2) was developed in the VFM crystallized samples as well as in the conventionally crystallized samples as x-ray diffraction (XRD) confirmed, the structural units of SiO4 tetrahedra (Q species) in the VFM crystallized samples were slightly different than the ones in conventionally crystallized samples as the Raman spectroscopy revealed. Moreover, the observed reduction in the crystallization time and apparent temperature in addition to the different crystallization mechanism observed in the VFM process both provided experimental evidence to support the presence of the microwave effect in the LS2 crystallization process. Also, the molecular orbital model was successfully used to predict the microwave absorption in LS2 glass and glass-ceramic. This model was consistent with experiments and indicated that microwave-material interactions were highly dependent on the structure of the material. Finally, a correlation between the Fourier transform infrared reflectance spectroscopy (FTIRRS) peak intensities and the volume fraction of crystals in partially crystallized LS2 glass samples was established.
- Densification Behavior of Ceramic and Crystallizable Glass Materials Constrained on a Rigid SubstrateCalata, Jesus Noel (Virginia Tech, 2005-05-04)Constrained sintering is an important process for many applications. The sintering process almost always involves some form of constraint, both internal and external, such as rigid particles, reinforcing fibers and substrates to which the porous body adheres. The densification behavior of zinc oxide and cordierite-base crystallizable glass constrained on a rigid substrate was studied to add to the understanding of the behavior of various materials undergoing sintering when subjected to external substrate constraint. Porous ZnO films were isothermally sintered at temperatures between 900°C and 1050°C. The results showed that the densification of films constrained on substrates is severely reduced. This was evident in the sintered microstructures where the particles are joined together by narrower necks forming a more open structure, instead of the equiaxed grains with wide grain boundaries observed in the freestanding films. The calculated activation energies of densification were also different. For the density range of 60 to 64%, the constrained film had an activation energy of 391 ± 34 kJ/mole compared to 242 ± 21 kJ/mole for the freestanding film, indicating a change in the densification mechanism. In-plane stresses were observed during the sintering of the constrained films. Yielding of the films, in which the stresses dropped slight or remained unchanged, occurred at relative densities below 60% before the stresses climbed linearly with increasing density followed by a gradual relaxation. A substantial amount of the stresses remained after cooling. Free and constrained films of the cordierite-base crystallizable glass (glass-ceramic) were sintered between 900°C and 1000°C. The substrate constraint did not have a significant effect on the densification rate but the constrained films eventually underwent expansion. Calculations of the densification activation energy showed that, on average, it was close to 1077 kJ/mole, the activation energy of the glass, indicating that the prevailing mechanism was still viscous flow. The films expanded earlier and faster with increasing sintering temperature. The expansion was traced to the formation of pores at the interface with the silicon substrate and to a lesser extent on aluminum nitride. It was significantly reduced when the silicon substrate was pre-oxidized at 900°C, leading to the conclusion that the pore formation at the interface was due to poor wetting, which in turn was caused by the loss of the thin oxide layer through a reaction with the glass.
- Design and Analyses of a Dimple Array Interconnect Technique for Power Electronics PackagingWen, Sihua (Virginia Tech, 2002-08-02)This research developed a novel, non-wire bond semiconductor interconnect technology, termed the Dimple Array interconnect (DAI), with significantly improved electrical, thermal and mechanical characteristics for power electronics applications. In the DAI structure, electrical connections onto the devices are achieved by solder bumps formed between the silicon device and arrays of dimples stamped on a metal sheet flex. This research first presents the design of the materials, electrical and thermal performance, reliability, and the fabrication process of the DAI. It was found that due to the use of solder material, the current handling capability and thermal management of Dimple Array interconnected devices are significantly better than those using wire bonds. In addition, the shorter and wider solder joints reduce parasitics, which is a serious problem in wire bond interconnects. The proposed fabrication process of the DAI is simpler than other developing integrated power packaging technologies, such as flip chip and deposited metallization integration. DAI was successfully demonstrated in a half-bridge power electronics module with much improved electrical characteristics. The study then focuses on the thermomechanical reliability of Dimple Array packages as compared to conventional controlled collapse bonding (CCB) flip chip packages. Experimental approaches, such as power cycling and temperature cycling tests, and numerical simulation with the help of finite element analysis (FEA) were used. The thermal cycling test shows that dimple solder joints display an eightfold reliability improvement over the conventional CCB solder joints. The power cycling test showed that the measured forward voltage can not reliably reflect the integrity of the solder joint interconnect. However, from metallographic cross-section images of these samples, it was concluded that the DAI solder joints are more reliable than the CCB solder joints under power cycling conditions. FEA results showed excellent correlation with experiments in predicting that the Dimple Array solder joints are more fatigue-resistant due to a reduced stress/strain concentration. Furthermore, failure mechanisms were explored using the mapped stress/strain distribution within the models. It was found that the CCB solder joint has a highly localized strain concentration at the device/solder interface, while strains are more uniformly distributed over the whole Dimple Array solder joint.
- Design and Analysis of Whispering Gallery Mode Semiconductor LasersHajjiah, Ali T. (Virginia Tech, 2009-01-19)Significant technical barriers currently prevent the wide spread adoption of WGM lasers as building blocks in large-scale photonic integrated circuits. The first challenge is to reduce the electrical power consumption at desirable levels of light output power. The second target is to obtain directional light emission without sacrificing other laser performance metrics. The best opportunity for success lies in the pursuit of small micro-Pillar lasers with spiral-geometry cavities. Process technology has been demonstrated for making high-performance WGM lasers including a refined ICP etching process for fabricating micro-Pillar cavities with sidewall roughness less than 10 nm and a new hydrogenation based approach to achieving current blocking that is compatible with all other processing steps and robust in comparison with earlier reports. A comprehensive photo-mask has been designed that enables investigation of the interplay between device geometry and WGM laser performance. Emphasis has been placed on enabling experiments to determining the impact of diffraction and scattering losses, current and carrier confinement, and surface recombination on electrical/optical device characteristics. In addition, a methodology has been developed for separating out process optimization work from the task of identifying the best means for directional light out-coupling. Our device fabrication methods can be proven on WGM lasers with pure cylindrical symmetry, hence results from these experiments should be independent of any specific light output coupling scheme. Particular attention has been paid to the fact that device geometries that give the best performance for purely symmetrical cavities may not yield the highest level of light emission from the spiral output notch. Such considerations seem to be missing from much of the earlier work reported in the literature. Finally, our processing techniques and device designs have resulted in individual WGM lasers that outperform those made by competitors. These devices have been incorporated into multi-element, coupled-cavity optical circuits thereby laying the groundwork for construction of digital photonic gates that execute AND, OR, and NOT logic functions.
- Design of High-density Transformers for High-frequency High-power ConvertersShen, Wei (Virginia Tech, 2006-07-13)Moore's Law has been used to describe and predict the blossom of IC industries, so increasing the data density is clearly the ultimate goal of all technological development. If the power density of power electronics converters can be analogized to the data density of IC's, then power density is a critical indicator and inherent driving force to the development of power electronics. Increasing the power density while reducing or keeping the cost would allow power electronics to be used in more applications. One of the design challenges of the high-density power converter design is to have high-density magnetic components which are usually the most bulky parts in a converter. Increasing the switching frequency to shrink the passive component size is the biggest contribution towards increasing power density. However, two factors, losses and parasitics, loom and compromise the effect. Losses of high-frequency magnetic components are complicated due to the eddy current effect in magnetic cores and copper windings. Parasitics of magnetic components, including leakage inductances and winding capacitances, can significantly change converter behavior. Therefore, modeling loss and parasitic mechanism and control them for certain design are major challenges and need to be explored extensively. In this dissertation, the abovementioned issues of high-frequency transformers are explored, particularly in regards to high-power converter applications. Loss calculations accommodating resonant operating waveform and Litz wire windings are explored. Leakage inductance modeling for large-number-of-stand Litz wire windings is proposed. The optimal design procedure based on the models is developed.
- Design Verification for Sequential Systems at Various Abstraction LevelsZhang, Liang (Virginia Tech, 2005-01-27)With the ever increasing complexity of digital systems, functional verification has become a daunting task to circuit designers. Functional verification alone often surpasses 70% of the total development cost and the situation has been projected to continue to worsen. The most critical limitations of existing techniques are the capacity issue and the run-time issue. This dissertation addresses the functional verification problem using a unified approach, which utilizes different core algorithms at various abstraction levels. At the logic level, we focus on incorporating a set of novel ideas to existing formal verification approaches. First, we present a number of powerful optimizations to improve the performance and capacity of a typical SAT-based bounded model checking framework. Secondly, we present a novel method for performing dynamic abstraction within a framework for abstraction-refinement based model checking. Experiments on a wide range of industrial designs have shown that the proposed optimizations consistently provide between 1-2 orders of magnitude speedup and can be extremely useful in enhancing the efficacy of existing formal verification algorithms. At the register transfer level, where the formal verification is less likely to succeed, we developed an efficient ATPG-based validation framework, which leverages the high-level circuit information and an improved observability-enhanced coverage to generate high quality validation sequences. Experiments show that our approach is able to generate high quality validation vectors, which achieve both high tag coverage and high bug coverage with extremely low computational cost.