Design and Analyses of a Dimple Array Interconnect Technique for Power Electronics Packaging
This research developed a novel, non-wire bond semiconductor interconnect technology, termed the Dimple Array interconnect (DAI), with significantly improved electrical, thermal and mechanical characteristics for power electronics applications. In the DAI structure, electrical connections onto the devices are achieved by solder bumps formed between the silicon device and arrays of dimples stamped on a metal sheet flex.
This research first presents the design of the materials, electrical and thermal performance, reliability, and the fabrication process of the DAI. It was found that due to the use of solder material, the current handling capability and thermal management of Dimple Array interconnected devices are significantly better than those using wire bonds. In addition, the shorter and wider solder joints reduce parasitics, which is a serious problem in wire bond interconnects. The proposed fabrication process of the DAI is simpler than other developing integrated power packaging technologies, such as flip chip and deposited metallization integration. DAI was successfully demonstrated in a half-bridge power electronics module with much improved electrical characteristics.
The study then focuses on the thermomechanical reliability of Dimple Array packages as compared to conventional controlled collapse bonding (CCB) flip chip packages. Experimental approaches, such as power cycling and temperature cycling tests, and numerical simulation with the help of finite element analysis (FEA) were used. The thermal cycling test shows that dimple solder joints display an eightfold reliability improvement over the conventional CCB solder joints. The power cycling test showed that the measured forward voltage can not reliably reflect the integrity of the solder joint interconnect. However, from metallographic cross-section images of these samples, it was concluded that the DAI solder joints are more reliable than the CCB solder joints under power cycling conditions. FEA results showed excellent correlation with experiments in predicting that the Dimple Array solder joints are more fatigue-resistant due to a reduced stress/strain concentration. Furthermore, failure mechanisms were explored using the mapped stress/strain distribution within the models. It was found that the CCB solder joint has a highly localized strain concentration at the device/solder interface, while strains are more uniformly distributed over the whole Dimple Array solder joint.