VTechWorks Repository :: Browsing by Author "Plassmann, Paul E."

Browsing by Author "Plassmann, Paul E."

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Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies
Linford, John Christian (Virginia Tech, 2010-05-05)
The new generations of multi-core chipset architectures achieve unprecedented levels of computational power while respecting physical and economical constraints. The cost of this power is bewildering program complexity. Atmospheric modeling is a grand-challenge problem that could make good use of these architectures if they were more accessible to the average programmer. To that end, software tools and programming methodologies that greatly simplify the acceleration of atmospheric modeling and simulation with emerging multi-core technologies are developed. A general model is developed to simulate atmospheric chemical transport and atmospheric chemical kinetics. The Cell Broadband Engine Architecture (CBEA), General Purpose Graphics Processing Units (GPGPUs), and homogeneous multi-core processors (e.g. Intel Quad-core Xeon) are introduced. These architectures are used in case studies of transport modeling and kinetics modeling and demonstrate per-kernel speedups as high as 40x. A general analysis and code generation tool for chemical kinetics called "KPPA" is developed. KPPA generates highly tuned C, Fortran, or Matlab code that uses every layer of heterogeneous parallelism in the CBEA, GPGPU, and homogeneous multi-core architectures. A scalable method for simulating chemical transport is also developed. The Weather Research and Forecasting Model with Chemistry (WRF-Chem) is accelerated with these methods with good results: real forecasts of air quality are generated for the Eastern United States 65% faster than the state-of-the-art models.
Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity
Chandrasekharan, Athira (Virginia Tech, 2010-08-05)
FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We approach the problem in a different way for development environments in which some circuit speed and area optimization may be sacrificed for improved implementation and debug turnaround. The PATIS floorplanner enables dynamic modular design, which accelerates non-local changes to the physical layout arising from design exploration and the addition of debug circuitry. We focus in this work on incremental and speculative floorplanning in PATIS, to accommodate minor design changes and to proactively generate possible floorplan variants. Current floorplan topology is preserved to minimize ripple effects and maintain reasonable module aspect ratios. The design modules are run-time reconfigurable to enable concurrent module implementation by independent invocations of the standard FPGA tools running on separate cores or hosts.
Activity Recognition using Singular Value Decomposition
Jolly, Vineet Kumar (Virginia Tech, 2006-08-08)
A wearable device that accurately records a user's daily activities is of substantial value. It can be used to enhance medical monitoring by maintaining a diary that lists what a person was doing and for how long. The design of a wearable system to record context such as activity recognition is influenced by a combination of variables. A flexible yet systematic approach for building a software classification environment according to a set of variables is described. The integral part of the software design is the use of a unique robust classifier that uses principal component analysis (PCA) through singular value decomposition (SVD) to perform real-time activity recognition. The thesis describes the different facets of the SVD-based approach and how the classifier inputs can be modified to better differentiate between activities. This thesis presents the design and implementation of a classification environment used to perform activity detection for a wearable e-textile system.
An Analysis of an Interrupt-Driven Implementation of the Master-Worker Model with Application-Specific Coprocessors
Hickman, Joseph (Virginia Tech, 2007-11-12)
In this thesis, we present a versatile parallel programming model composed of an individual general-purpose processor aided by several application-specific coprocessors. These computing units operate under a simplification of the master-worker model. The user-defined coprocessors may be either homogeneous or heterogeneous. We analyze system performance with regard to system size and task granularity, and we present experimental results to determine the optimal operating conditions. Finally, we consider the suitability of this approach for scientific simulations — specifically for use in agent-based models of biological systems.
An Application Framework for a Power-Aware Processor Architecture
Mandlekar, Anup Shrikant (Virginia Tech, 2012-08-07)
The instruction-set based general purpose processors are not energy-efficient for event-driven applications. The E-textiles group at Virginia Tech proposed a novel data-flow processor architecture design to bridge the gap between event-driven applications and the target architecture. The architecture, although promising in terms of performance and energy-efficiency, was explored for limited number of applications. This thesis presents a model-driven approach for the design of an application framework, facilitating rapid development of software applications to test the architecture performance. The application framework is integrated with the prior automation framework bringing software applications at the right level of abstraction. The processor architecture design is made flexible and scalable, making it suitable for a wide range of applications. Additionally, an embedded flash memory based architecture design for reduction in the static power consumption is proposed. This thesis estimates significant reduction in overall power consumption with the incorporation of flash memory.
Automated Landing Site Evaluation for Semi-Autonomous Unmanned Aerial Vehicles
Klomparens, Dylan (Virginia Tech, 2008-08-20)
A system is described for identifying obstacle-free landing sites for a vertical-takeoff-and-landing (VTOL) semi-autonomous unmanned aerial vehicle (UAV) from point cloud data obtained from a stereo vision system. The relatively inexpensive, commercially available Bumblebee stereo vision camera was selected for this study. A "point cloud viewer" computer program was written to analyze point cloud data obtained from 2D images transmitted from the UAV to a remote ground station. The program divides the point cloud data into segments, identifies the best-fit plane through the data for each segment, and performs an independent analysis on each segment to assess the feasibility of landing in that area. The program also rapidly presents the stereo vision information and analysis to the remote mission supervisor who can make quick, reliable decisions about where to safely land the UAV. The features of the program and the methods used to identify suitable landing sites are presented in this thesis. Also presented are the results of a user study that compares the abilities of humans and computer-supported point cloud analysis in certain aspects of landing site assessment. The study demonstrates that the computer-supported evaluation of potential landing sites provides an immense benefit to the UAV supervisor.
ByteSTM: Java Software Transactional Memory at the Virtual Machine Level
Mahmoud Mohamedin, Mohamed Ahmed (Virginia Tech, 2012-02-08)
As chip vendors are increasingly manufacturing a new generation of multi-processor chips called multicores, improving software performance requires exposing greater concurrency in software. Since code that must be run sequentially is often due to the need for synchronization, the synchronization abstraction has a significant effect on program performance. Lock-based synchronization — the most widely used synchronization method — suffers from programability, scalability, and composability challenges. Transactional memory (TM) is an emerging synchronization abstraction that promises to alleviate the difficulties with lock-based synchronization. With TM, code that read/write shared memory objects is organized as transactions, which speculatively execute. When two transactions conflict (e.g., read/write, write/write), one of them is aborted, while the other commits, yielding (the illusion of) atomicity. Aborted transactions are re-started, after rolling-back changes made to objects. In addition to a simple programming model, TM provides performance comparable to lock-based synchronization. Software transactional memory (STM) implements TM entirely in software, without any special hardware support, and is usually implemented as a library, or supported by a compiler or by a virtual machine. In this thesis, we present ByteSTM, a virtual machine-level Java STM implementation. ByteSTM implements two STM algorithms, TL2 and RingSTM, and transparently supports implicit transactions. Program bytecode is automatically modified to support transactions: memory load/store bytecode instructions automatically switch to transactional mode when a transaction starts, and switch back to normal mode when the transaction successfully commits. Being implemented at the VM-level, it accesses memory directly and uses absolute memory addresses to uniformly handle memory. Moreover, it avoids Java garbage collection (which has a negative impact on STM performance), by manually allocating and recycling memory for transactional metadata. ByteSTM uses field-based granularity, and uses the thread header to store transactional metadata, instead of the slower Java ThreadLocal abstraction. We conducted experimental studies comparing ByteSTM with other state-of-the-art Java STMs including Deuce, ObjectFabric, Multiverse, DSTM2, and JVSTM on a set of micro- benchmarks and macro-benchmarks. Our results reveal that, ByteSTM's transactional throughput improvement over competitors ranges from 20% to 75% on micro-benchmarks and from 36% to 100% on macro-benchmarks.
Chemotaxis in Densely Populated Tissue Determines Germinal Center Anatomy and Cell Motility: A New Paradigm for the Development of Complex Tissues
Hawkins, Jared B.; Jones, Mark T.; Plassmann, Paul E.; Thorley-Lawson, David A. (PLOS, 2011-12-01)
Germinal centers (GCs) are complex dynamic structures that form within lymph nodes as an essential process in the humoral immune response. They represent a paradigm for studying the regulation of cell movement in the development of complex anatomical structures. We have developed a simulation of a modified cyclic re-entry model of GC dynamics which successfully employs chemotaxis to recapitulate the anatomy of the primary follicle and the development of a mature GC, including correctly structured mantle, dark and light zones. We then show that correct single cell movement dynamics (including persistent random walk and inter-zonal crossing) arise from this simulation as purely emergent properties. The major insight of our study is that chemotaxis can only achieve this when constrained by the known biological properties that cells are incompressible, exist in a densely packed environment, and must therefore compete for space. It is this interplay of chemotaxis and competition for limited space that generates all the complex and biologically accurate behaviors described here. Thus, from a single simple mechanism that is well documented in the biological literature, we can explain both higher level structure and single cell movement behaviors. To our knowledge this is the first GC model that is able to recapitulate both correctly detailed anatomy and single cell movement. This mechanism may have wide application for modeling other biological systems where cells undergo complex patterns of movement to produce defined anatomical structures with sharp tissue boundaries.
Collaborative Scheduling and Synchronization of Distributable Real-Time Threads
Fahmy, Sherif Fadel (Virginia Tech, 2010-05-05)
In this dissertation, we consider the problem of scheduling and synchronization of distributable real-time threads --- Real-Time CORBA's first-class abstraction for programming real-time, multi-node sequential behaviors. Distributable real-time threads can be scheduled, broadly, using two paradigms: node independent scheduling, in which nodes independently construct thread schedules, based on node-level decomposition of distributable thread (or DT) scheduling parameters, and collaborative scheduling, in which nodes collaborate to construct system-wide thread schedules, which may or may not involve scheduling parameter decomposition. While significant literature exists on node independent scheduling, little is known about collaborative scheduling and its concomitant tradeoffs. We design three collaborative scheduling algorithms, called ACUA, QBUA, and DQBUA. ACUA uses theory of consensus and QBUA uses theory of quorums for distributable thread schedule construction. DQBUA extends QBUA with lock-based, local and distributed concurrency control. The algorithms consider a model where distributable threads arrive arbitrarily, have time/utility function time constraints, access resources in an arbitrary way (e.g., arbitrary lock acquire/release order, arbitrary nestings), and are subject to arbitrary node crash failures and message losses. We analytically establish several properties of the algorithms including probabilistic end-to-end termination time satisfactions, timeliness optimality during underloads, bounded exception handling time, and correctness of the algorithms in partially synchronous systems. We implement distributable real-time threads in the Linux kernel as a first-class programming and scheduling abstraction. The resulting kernel, called ChronOS, provides application interfaces for creating and manipulating distributable threads, as well as kernel interfaces and mechanisms for scheduling them (using both independent and collaborative approaches). ChronOS also has failure detector mechanisms for detecting and recovering from distributable thread failures. We implement the proposed scheduling algorithms and their competitors in ChronOS and compare their behavior. Our studies reveal that the collaborative scheduling algorithms are superior to independent scheduling algorithms for certain thread sets, in particular, when thread sections have significantly varying execution time. This variability, especially if the variability is not consistent among the threads, may cause each node to make conflicting decisions in the absence of global information. We observe that collaborative schedulers outperform independent schedulers (e.g., EDF augmented with PIP) in terms of accrued utility by as much as 75%. We identify distributed dependencies as one of the major sources of overhead in collaborative scheduling. In particular, the cost of distributed lock-based concurrency control (e.g., lock management, distributed deadlock detection/resolution) can significantly reduce the problem space for which collaborative scheduling is beneficial. To mitigate this, we consider the use of software transactional memory (or STM), an optimistic, non-blocking synchronization alternative to lock-based concurrency control which has been extensively studied in non real-time contexts. We consider distributable real-time threads with STM concurrency control, and develop techniques for analyzing and bounding their end-to-end response times on distributed single-processor and distributed multiprocessor systems. We also develop contention management techniques, a key component of STM, which are driven by threads' real-time scheduling parameters, and establish their tradeoffs against non-real-time contention managers.
Context-Aware Resource Management and Performance Analysis of Millimeter Wave and Sub-6 GHz Wireless Networks
Semiari, Omid (Virginia Tech, 2017-08-28)
Emerging wireless networks are foreseen as an integration of heterogeneous spectrum bands, wireless access technologies, and backhaul solutions, as well as a large-scale interconnection of devices, people, and vehicles. Such a heterogeneity will range from the proliferation of multi-tasking user devices with different capabilities such as smartphones and tablets to the deployment of multi-mode access points that can operate over heterogeneous frequency bands spanning both sub-6 GHz microwave and high-frequency millimeter wave (mmW) frequencies bands. This heterogeneous ecosystem will yield new challenges and opportunities for wireless resource management. On the one hand, resource management can exploit user and network-specific context information, such as application type, social metrics, or operator pricing, to develop application-driven, context-aware networks. Similarly, multiple frequency bands can be leveraged to meet the stringent and heterogeneous quality-of-service (QoS) requirements of the new wireless services such as video streaming and interactive gaming. On the other hand, resource management in such heterogeneous, multi-band, and large-scale wireless systems requires distributed frameworks that can effectively utilize all available resources while operating with manageable overhead. The key goal of this dissertation is therefore to develop novel, self-organizing, and low-complexity resource management protocols -- using techniques from matching theory, optimization, and machine learning -- to address critical resource allocation problems for emerging heterogeneous wireless systems while explicitly modeling and factoring diverse network context information. Towards achieving this goal, this dissertation makes a number of key contributions. First, a novel context-aware scheduling framework is developed for enabling dual-mode base stations to efficiently and jointly utilize mmW and microwave frequency resources while maximizing the number of user applications whose stringent delay requirements are satisfied. The results show that the proposed approach will be able to significantly improve the QoS per application and decrease the outage probability. Second, novel solutions are proposed to address both network formation and resource allocation problems in multi-hop wireless backhaul networks that operate at mmW frequencies. The proposed framework motivates collaboration among multiple network operators by resource sharing to reduce the cost of backhauling, while jointly accounting for both wireless channel characteristics and economic factors. Third, a novel framework is proposed to exploit high-capacity mmW communications and device-level caching to minimize handover failures as well as energy consumption by inter-frequency measurements, and to provide seamless mobility in dense heterogeneous mmW-microwave small cell networks (SCNs). Fourth, a new cell association algorithm is proposed, based on matching theory with minimum quota constraints, to optimize load balancing in integrated mmW-microwave networks. Fifth, a novel medium access control (MAC) protocol is proposed to dynamically manage the wireless local area network (WLAN) traffic jointly over the unlicensed 60 GHz mmW and sub-6 GHz bands to maximize the saturation throughput and minimize the delay experienced by users. Finally, a novel resource management approach is proposed to optimize device-to-device (D2D) communications and improve traffic offload in heterogeneous wireless SCNs by leveraging social context information that is dynamically learned by the network. In a nutshell, by providing novel, context-aware, and self-organizing frameworks, this dissertation addresses fundamentally challenging resource management problems that mainly stem from large scale, stringent service requirements, and heterogeneity of next-generation wireless networks.
Design and Analysis of a Real-time Data Monitoring Prototype for the LWA Radio Telescope
Vigraham, Sushrutha (Virginia Tech, 2011-02-01)
Increasing computing power has been helping researchers understand many complex scientific problems. Scientific computing helps to model and visualize complex processes such as molecular modelling, medical imaging, astrophysics and space exploration by processing large set of data streams collected through sensors or cameras. This produces a massive amount of data which consume a large amount of processing and storage resources. Monitoring the data streams and filtering unwanted information will enable efficient use of the available resources. This thesis proposes a data-centric system that can monitor high-speed data streams in real-time. The proposed system provides a flexible environment where users can plug-in application-specific data monitoring algorithms. The Long Wavelength Array telescope (LWA) is an astronomical apparatus that works with high speed data streams, and the proposed data-centric platform is developed to evaluate FPGAs to implement data monitoring algorithms in LWA. The throughput of the data-centric system has been modeled and it is observed that the developed data-centric system can deliver a maximum throughput of 164 MB/s.
Design and prototyping of Hardware-Accelerated Locality-aware Memory Compression
Srinivas, Raghavendra (Virginia Tech, 2020-09-09)
Hardware Acceleration is the most sought technique in chip design to achieve better performance and power efficiency for critical functions that may be in-efficiently handled from traditional OS/software. As technology started advancing with 7nm products already in the market which can provide better power and performance consuming low area, the latency-critical functions that were handled by software traditionally now started moving as acceleration units in the chip. This thesis describes the accelerator architecture, implementation, and prototype for one of such functions namely "Locality-Aware memory compression" which is part of the "OS-controlled memory compression" scheme that has been actively deployed in today's OSes. In brief, OS-controlled memory compression is a new memory management feature that transparently, dramatically, and adaptively increases effective main memory capacity on-demand as software-level memory usage increases beyond physical memory system capacity. OS-controlled memory compression has been adopted across almost all OSes (e.g., Linux, Windows, macOS, AIX) and almost all classes of computing systems (e.g., smartphones, PCs, data centers, and cloud). The OS-controlled memory compression scheme is Locality Aware. But still under OS-controlled memory compression today, applications experience long-latency page faults when accessing compressed memory. To solve this per- performance bottle-neck, acceleration technique has been proposed to manage "Locality Aware Memory compression" within hardware thereby enabling applications to access their OS- compressed memory directly. This Accelerator is referred to as HALK throughout this work, which stands for "Hardware-accelerated Locality-aware Memory Compression". The literal mean- ing of the word HALK in English is 'a hidden place'. As such, this accelerator is neither exposed to the OS nor to the running applications. It is hidden entirely in the memory con- troller hardware and incurs minimal hardware cost. This thesis work explores developing FPGA design prototype and gives the proof of concept for the functionality of HALK by running non-trivial micro-benchmarks. This work also provides and analyses power, performance, and area of HALK for ASIC designs (at technology node of 7nm) and selected FPGA Prototype design.
Design and Verification of Privacy and User Re-authentication Systems
Jagadeesan, Harini (Virginia Tech, 2009-04-30)
In the internet age, privacy and security have become major concerns since an increasing number of transactions are made over an unsecured network. Thus there is a greater chance for private data to be misused. Further, insider attacks can result in loss of valuable data. Hence there arises a strong need for continual, non-intrusive, quick user re-authentication. Previously, a number of studies have been conducted on authentication using behavioral attributes. Currently, few successful re-authentication mechanisms are available since they use either the mouse or the keyboard for re-authentication and target particular applications. However, successful re-authentication is still dependent on a large number of factors such as user excitation level, fatigue and using just the keyboard or the mouse does not mitigate these factors successfully. Both keyboard and mouse contain valuable, hard-to-duplicate information about the user's behavior. This can be used for analysis and identification of the current user. We propose an application independent system that uses this information for user re-authentication. This system will authenticate the user continually based on his/her behavioral attributes obtained from both the keyboard and mouse operations. This re-authentication system is simple, continual, non-intrusive and easily deployable. To utilize the mouse and keyboard information for re-authentication, we propose a novel heuristic that uses the percentage of mouse-to-keyboard interaction ratio. This heuristic allows us to extract suitable user-behavioral attributes. The extracted data is compared with an already trained database for user re-authentication. The accuracy of the system is calculated by the number of correct identifications to total number of identifications. At present, the accuracy of the system is around 96% for application based user re-authentication and around 82% for application independent user re-authentication. We perform black box, white box testing and Spec# verification procedures that prove the robustness of the proposed system. On testing POCKET, a privacy protection software for children, it was found that the security of POCKET was inadequate at the user level. Our system enhances POCKET security at the user level and ensures that the child's privacy is protected.
Design of a Multibus Data-Flow Processor Architecture
Malayattil, Sarosh Aravind (Virginia Tech, 2012-02-17)
General purpose microcontrollers have been used as computational elements in various spheres of technology. Because of the distinct requirements of specific application areas, however, general purpose microcontrollers are not always the best solution. There is a need for specialized processor architectures for specific application areas. This thesis discusses the design of such a specialized processor architecture targeted towards event driven sensor applications. This thesis presents an augmented multibus dataflow processor architecture and an automation framework suitable for executing a range of event driven applications in an energy efficient manner. The energy efficiency of the multibus processor architecture is demonstrated by comparing the energy usage of the architecture with that of a PIC12F675 microcontroller.
Design of a Power-aware Dataflow Processor Architecture
Narayanaswamy, Ramya Priyadharshini (Virginia Tech, 2010-07-20)
In a sensor monitoring embedded computing environment, the data from a sensor is an event that triggers the execution of an application. A sensor node consists of multiple sensors and a general purpose processor that handles the multiple events by deploying an event-driven software model. The software overheads of the general purpose processors results in energy inefficiency. What is needed is a class of special purpose processing elements which are more energy efficient for the purpose of computation. In the past, special purpose microcontrollers have been designed which are energy efficient for the targeted application space. However, reuse of the same design techniques is not feasible for other application domains. Therefore, this thesis presents a power-aware dataflow processor architecture targeted for the electronic textile computing space. The processor architecture has no instructions, and handles multiple events inherently without deploying software methods. This thesis also shows that the power-aware implementation reduces the overall static power consumption.
Design of an Automation Framework for a Novel Data-Flow Processor Architecture
Lakshmanan, Karthick (Virginia Tech, 2010-07-21)
Improved process technology has resulted in the integration of computing elements into multiple application areas. General purpose micro-controllers are designed to assist in this integration through a flexible design. The application areas, however, are so diverse in nature that the general purpose micro-controllers may not provide a suitable abstraction for all classes of applications. There is a need for specially designed architectures in application areas where the general purpose micro-controllers suffer from inefficiencies. This thesis focuses in the design of a processor architecture that provides a suitable design abstraction for a class of periodic, event-driven embedded applications such as sensor-monitoring systems. The design principles of the processor architecture are focused on the target application requirements, which are identified as event-driven nature with concurrent task execution and deterministic timing behavior. Additionally, to reduce the design complexity of applications on this novel architecture, an automation framework has been implemented. This thesis presents the design of the processor architecture and the automation framework explaining the suitability of the designed architecture for the target applications. The energy use of the novel architecture is compared with that of PIC12F675 micro-controller to demonstrate the energy-efficiency of the designed architecture.
Design Optimization of Hybrid Switch Soft-Switching Inverters using Multi-Scale Electro-Thermal Simulation
Reichl, John Vincent (Virginia Tech, 2015-11-17)
The development of a fully automated tool that is used to optimize the design of a hybrid switch soft-switching inverter using a library of dynamic electro-thermal component models parameterized in terms of electrical, structural and material properties is presented. A multi-scale electro-thermal simulation approach is developed allowing for a large number of parametric studies involving multiple design variables to be considered, drastically reducing simulation time. Traditionally, electro-thermal simulation and analysis has been used to predict the behavior of pre-existing designs. While the traditional approach to electro-thermal analysis can help shape cooling requirements and heat sink designs to maintain certain junction temperatures, there is no guarantee that the design under study is the most optimal. This dissertation uses electro-thermal simulation to guarantee an optimal design and thus truly minimizing cooling requirements and improving device reliability. The proposed optimization tool is used to provide a step-by-step design optimization of a two-coupled magnetic hybrid soft-switching inverter. The soft-switching inverter uses a two-coupled magnetic approach for transformer reset condition [1], a variable timing control for achieving ZVS over the entire load range [2], and utilizes a hybrid switch approach for the main device [3]. Design parameters such as device chip area, gate drive timing control and external resonant capacitor and inductor are used to minimize device loss subject to design constraints such as converter minimum on-time, maximum device chip area, and transformer reset condition. Since the amount of heat that is dissipated has been minimized, the optimal cooling requirements can be determined by reducing the cooling convection coefficients until desired junction temperatures are achieved. The optimized design is then compared and contrasted with an already existing design from the Virginia Tech freedom car project using the generation II module. It will be shown that the proposed tool improves the baseline design by 16% in loss and reduces the cooling requirements by 42%. Validation of the device model against measured data along with the procedures for device parameter extraction is also provided. Validation of the thermal model against measured data is also provided.
Development and Analysis of a Spiral Theory-based Cybersecurity Curriculum
Back, Godmar V.; Basu, Debarati; Naciri, William; Lohani, Vinod K.; Plassmann, Paul E.; Barnette, Dwight; Ribbens, Calvin J.; Gantt, Kira; McPherson, David (2017-01-09)
Enhance cybersecurity learning experiences of students at Virginia Tech’s large engineering program
Directional Perception of Force in a Virtual Reality Environment
Long, Zihao (Virginia Tech, 2020-05-08)
Force feedback during teleoperation and in Virtual Reality (VR) environments is becoming increasingly common. We are interested in understanding the impact of motion on the directional accuracy of force perception, as observed in a VR environment. We used a custom force-feedback system that pulled a handle with a force of 1.87N at various angles in front of N=14 subjects. The virtual environment showed a curved wall, which corresponded to the locations from which the force could physically originate. Subjects selected where they perceived the force to originate from with a virtual laser pointer and by orienting their head. We compared several conditions: the subject held the handle still; the subject moved the handle back and forth toward the center of the wall; the subject moved the handle back and forth across their body; and the subject moved the handle back and forth toward where they thought the force was originating. Subjects were able to localize the force with an average accuracy of 1-10 degrees depending on the force's location, which is better than previous studies. All conditions had similiar accuracies. Subjects had the best precision when they followed the force as compared to either of the other conditions with movement.
Domain Adaptation with a Classifier Trained by Robust Pseudo-Labels
Zhou, Yunke (Virginia Tech, 2022-01-07)
With the rapid growth of computing power, approaches based on deep learning algorithms have achieved remarkable results in solving computer vision classification problems. These performance improvements are achieved by assuming the source and target data are collected from the same probability distribution. However, this assumption is usually too strict to be satisfied in many real-world applications, such as big data analysis, natural language processing, and computer vision classification problems. Because of distribution discrepancies between these domains, directly training the model on the source domain cannot be expected to generate satisfactory results on the target domain. Therefore, the problem of minimizing these data distribution discrepancies is the main challenge with which modern machine learning is now faced. To address this problem, domain adaptation (DA) aims to identify domain-invariant features between two different but related domains. This thesis proposes a state-of-the-art DA approach that overcomes the limitations of traditional DA methods. To capture fine-grained information for each category, I deploy centroid-to-centroid alignment to perform domain adaptation. An Exponential Moving Average strategy (EMA) is used to ensure we can form robust source and target centroids. A Gaussian-uniform mixture model is trained using an Expectation-Maximization (EM) algorithm to infer the robustness of the target pseudo-labels. With the help of target pseudo-labels, I propose two novel types of classifiers: (1) a target-oriented classifier (TO); and (2) a centroid-oriented classifier (CO). Extensive experiments show that these two classifiers exhibit superior performance on a variety of DA benchmarks when compared to standard baseline methods.

Browsing by Author "Plassmann, Paul E."

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