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Virginia Tech Patents

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https://hdl.handle.net/10919/72294

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Browsing Virginia Tech Patents by Department "Electrical and Computer Engineering"

Now showing 1 - 20 of 51
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    Anti-islanding detection for three-phase distributed generation
    (United States Patent and Trademark Office, 2017-04-25)
    Wobbling the operating frequency of a phase-locked loop (PLL), preferably by adding a periodic variation is feedback gain or delay in reference signal phase allows the avoidance of any non-detection zone that might occur due to exact synchronization of the phase locked loop operating frequency with a reference signal. If the change in PLL operating frequency is periodic, it can be made of adequate speed variation to accommodate and time requirement for islanding detection or the like when a reference signal being tracked by the PLL is lost. Such wobbling of the PLL operating frequency is preferably achieved by addition a periodic variable gain in a feedback loop and/or adding a periodically varying phase delay in a reference signal and/or PLL output.
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    Avoiding internal switching loss in soft switching cascode structure device
    (United States Patent and Trademark Office, 2017-08-15)
    In a cascode switching device, avalanche breakdown of a control transistor and loss of soft switching or zero voltage switching in a high voltage normally-on depletion mode transistor having a negative switching threshold voltage and the corresponding losses are avoided by providing additional capacitance in parallel with a parallel connection of drain-source parasitic capacitance of the control transistor and gate-source parasitic capacitance of the high voltage, normally-on transistor to form a capacitive voltage divider with the drain-source parasitic capacitance of the high voltage, normally-on transistor such that the avalanche breakdown voltage of the control transistor cannot be reached. The increased capacitance also assures that the drain source parasitic capacitance of the high voltage, normally-on transistor is fully discharged before internal turn-on can occur.
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    Circuit and method for driving synchronous rectifiers for high-frequency flyback converters
    (United States Patent and Trademark Office, 2017-11-07)
    A voltage waveform similar to a waveform of a magnetizing current of an isolation transformer and immune to high frequency oscillatory resonant behavior is developed across a capacitor of a series resistor and capacitor connection connected in parallel with a synchronous rectifier. A simple logic circuit produces a waveform for controlling the synchronous rectifier which is not subject to significant turn on delay or early turn off caused by oscillatory resonances among parasitic inductances and capacitances. Improved timing accuracy of a synchronous converter provides improved power converter accuracy, particularly for flyback converters which are commonly used in converters for supplying power to offline electrical devices but are subject to oscillatory resonant behaviors that cannot be adequately damped at switching frequencies sufficiently high to support miniaturization of adapters.
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    Cognitive reconfigurable RF technology
    (United States Patent and Trademark Office, 2017-11-21)
    The present invention provides a radio architecture that contains a main radio path and a sensing path. The parameters of the main radio path are controlled by a cognitive engine. The main radio path is tuned to a desired frequency band. The sensing path is used to monitor the spectrum around the desired frequency band. To minimize effects of undesired non-linearity on sensing, sensing path may have a lower gain setting. The cognitive engine determines the optimal setting of the main RF front-end with respect to the current state of the spectrum.
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    Cooperative modulation of classification in cognitive radio networks
    (United States Patent and Trademark Office, 2016-11-22)
    Multiuser classification of the modulation schemes of simultaneous multiple unknown transmitters is disclosed. Cooperation among multiple cognitive radio receivers for modulation classification offers improvements in classification performance and overcomes detrimental channel effects that degrade single cognitive radio classifier performance. A centralized soft-combining data fusion algorithm based on the joint probability distribution of fourth order cumulants is presented for cooperative modulation classification. Fourth order cumulants of received signals are calculated as discriminating features for different modulation schemes at each cognitive radio node and sent to a centralized data node. The data node chooses the modulation scheme that maximizes the joint probability of the estimated cumulants.
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    Energy storage for power factor correction in battery charger for electric-powered vehicles
    (United States Patent and Trademark Office, 2018-03-13)
    Switches of a switching circuit used to control operation of an electric motor such as in an electrically powered vehicle connect respective windings of the electric motor as a single phase inductor during battery charging. The inductor can then store inherent low frequency, second order ripple power and return that power to a load presented by a battery during battery charging to deliver substantially constant current. Storage of ripple power in the inductor allows the capacitance value, size, weight and cost of a filter capacitor of a power factor correction circuit providing input power to a battery charger to be reduced by an order of magnitude or more. Direction of current flow through the inductor is periodically reversed to avoid magnetizing the motor.
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    Estimating the location of a wireless terminal based on radio-frequency pattern matching and cooperative measurements
    (United States Patent and Trademark Office, 2017-03-14)
    A method for estimating the location of a wireless terminal is disclosed that is based on using: the known location of one or more devices, empirical data that indicates the relative position of the wireless terminal to the devices, and empirical data that indicates the relative position of the wireless terminal (which is at an unknown location) relative to other wireless terminals that are also at unknown locations.
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    External ramp autotuning for current mode control of switching converter
    (United States Patent and Trademark Office, 2017-06-13)
    Peak current, valley current or average current mode controlled power converters in either digital or analog implementations obtain a stabilized feedback loop and allow high system bandwidth design by use of an external ramp generator using a slope computation equation or design parameters based on fixing the quality factor of a double pole at one-half of the switching frequency at a desired value The slope of the external ramp waveform is tuned automatically with knowledge of the slope change in the waveform of inductor current of a power converter derived by differentiating a waveform in the current feedback loop. This autotuning of the external ramp generator provides immunity of quality factor change under variations of duty cycle, component values of topological change of the power converter.
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    High frequency integrated point-of-load power converter with embedded inductor substrate
    (United States Patent and Trademark Office, 2017-02-07)
    A low profile power converter structure is provide wherein volume is reduced and power density is increased to approach 1 KW/in3 by at least one of forming an inductor as a body of magnetic material embedded in a substrate formed by a plurality of printed circuit board (PCB) lamina and forming inductor windings of PCB cladding and vias which may be of any desired number of turns and may include inversely coupled windings and which provide a lateral flux path, forming the body of magnetic material from high aspect ratio flakes of magnetic material which are aligned with the inductor magnetic field in an insulating organic binder and hot-pressed and providing a four-layer architecture comprising two layers of PCB lamina including the embedded body of magnetic material, a shield layer and an additional layer of PCB lamina, including cladding for supporting and connecting a switching circuit, a capacitor and the inductor.
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    Hybrid interleaving structure with adaptive phase locked loop for variable frequency controlled switching converter
    (United States Patent and Trademark Office, 2018-07-03)
    In a multi-phase power converter using a phase-locked loop (PLL) arrangement for interleaving of pulse frequency modulated (PFM) pulses of the respective phases, improved transient response, improved stability of high bandwidth output voltage feedback loop, guaranteed stability of the PLL loop and avoidance of jittering and phase cancellation issues are achieved by anchoring the bandwidth at the frequency of peak phase margin. This methodology is applicable to multi-phase power conveners of any number of phases and any known or foreseeable topology for individual phases and is not only applicable to power converters operating under constant on-time control, but is extendable to ramp pulse modulation (RPM) control and hysteresis control. Interleaving of pulses from all phases is simplified through use of phase managers with a reduced number of PLLS using hybrid interleaving arrangements that do not exhibit jittering even when ripple is completely canceled.
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    Iaverage current mode (ACM) control for switching power converters
    (United States Patent and Trademark Office, 2016-05-17)
    Providing a fast current sensor direct feedback path to a modulator for controlling switching of a switched power converter in addition to an integrating feedback path which monitors average current for control of a modulator provides fast dynamic response consistent with system stability and average current mode control. Feedback of output voltage for voltage regulation can be combined with current information in the integrating feedback path to limit bandwidth of the voltage feedback signal.
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    Low profile coupled inductor substrate with transient speed improvement
    (United States Patent and Trademark Office, 2018-10-23)
    A low profile inductor structure suitable for use in a high power density power converter has one or more windings formed by vias through a thin, generally planar body of magnetic material forming the inductor core and conductive cladding on the body of magnetic material or material covering the magnetic material body. Variation of inductance with load current and other operational or environmental parameters is reduced to any desired degree by forming a slot that removes all or a portion of the magnetic material between the locations of the vias.
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    Maximum power point tracking for solar panels
    (United States Patent and Trademark Office, 2017-06-20)
    Approximately one-half of the loss of delivered power from a solar panel having photovoltaic (PV) cells connected in series to form sub-panels due to shading is recovered at low hardware cost by connecting sub-panels in series and providing maximum power point tracking control in common for the series connected sub-panels such that the respective sub-panels produce equal voltages even in the presence of shading of a portion of one or more sub-panels. By doing so, the input voltage of respective power converters which control the voltage at which each sub-panel is operated can be placed close to the maximum power point of each sub-panel regardless of shading and maximum total power harvested even though the respective sub-panels are not operated at optimum voltages.
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    Metalorganic chemical vapor deposition of layered structure oxides
    (United States Patent and Trademark Office, 1995-12-26)
    A method of fabricating high quality layered structure oxide ferroelectric thin films. The deposition process is a chemical vapor deposition process involving chemical reaction between volatile metal organic compounds of various elements comprising the layered structure material to be deposited, with other gases in a reactor, to produce a nonvolatile solid that deposits on a suitably placed substrate such as a conducting, semiconducting, insulating, or complex integrated circuit substrate. The source materials for this process may include organometallic compounds such as alkyls, alkoxides, .beta.-diketonates or metallocenes of each individual element comprising the layered structure material to be deposited and oxygen. Preferably, the reactor in which the deposition is done is either a hot wall or a cold wall reactor and the vapors are introduced into this reactor either through a set of bubblers or through a direct liquid injection system. The ferroelectric films can be used for device applications such as in capacitors, dielectric resonators, heat sensors, transducers, actuators, nonvolatile memories, optical waveguides and displays.
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    Method and apparatus for current/power balancing
    (United States Patent and Trademark Office, 2017-02-28)
    Aspects of the disclosure provide a power circuit that includes a first switch circuit in parallel with a second switch circuit. The first switch circuit and the second switch circuit are coupled to a first driving node, a second driving node, a source node and a drain node via interconnections. The power circuit receives a control signal between the first driving node and the second driving node to control a current flowing from the drain node to the source node through the first switch circuit and the second switch circuit. In the power circuit, a first interconnection and a second interconnection of the interconnections are inductively coupled to balance the current flowing through the first switch circuit and the second switch circuit.
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    Method and apparatus for current/power balancing
    (United States Patent and Trademark Office, 2018-03-20)
    Aspects of the disclosure provide a system having a power circuit. The power circuit includes a first switch circuit having at least a first transistor and a second switch circuit having at least a second transistor. Further, the power circuit includes first interconnections configured to couple the first switch circuit to driving nodes, a source node and a drain node of the power circuit, and second interconnection configured to couple the second switch circuit in parallel to the first switch circuit to the driving nodes, the source node and the drain node of the power circuit. A polarity of unbalance in the first interconnections and the second interconnections dominates a polarity of current unbalance in the first switch circuit and the second switch circuit.
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    Method and apparatus for driving a power device
    (United States Patent and Trademark Office, 2016-12-27)
    Aspects of the disclosure provide a circuit for driving a power switch. The circuit includes a first circuit configured to provide a charging current to charge a control terminal of the power switch, a second circuit configured to provide a discharging current to discharge the control terminal of the power switch, and a control circuit configured to provide control signals to the first circuit and the second circuit to activate/deactivate the first circuit and the second circuit. At least one of the charging current and the discharging current ramps from a first level to a second level at a rate.
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    Method and apparatus to improve power device reliability
    (United States Patent and Trademark Office, 2017-05-23)
    Aspects of the disclosure provide a power device that includes an upper power module and a lower power module. The upper power module and the lower power module are coupled in series between two supply voltages, and are respectively controlled by a first control signal and a second control signal. Interconnections of the power device are inductively coupled to prevent reliability issues, such as crosstalk, self turn on, self sustained oscillation, and the like.
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    Method and system for dynamically obscuring addresses in IPv6
    (United States Patent and Trademark Office, 2016-10-04)
    The invention dynamically obscures network and transport layer addresses of packets to achieve anonymity, including authentication privacy, as well as protection against tracking and traffic correlation and certain classes of network attacks by combining both intrusion protection with anonymity, avoiding the use of a separate management unit outside the host for distribution of obscured addresses. The invention enables a host to automatically configure obscured addresses and determine the obscured address of the intended recipient without outside involvement, computing addresses based on a set of parameters, and to operate without re-authentication whenever an address changes. The invention enables encryption of the packet payload to prevent traffic correlation. The technology of the invention can be implemented embedded on a host device or as a connected gateway device and requires negligible configuration and is therefore transparent to hosts.
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    Method for reducing or eliminating conducted common mode noise in a transformer
    (United States Patent and Trademark Office, 2017-03-07)
    At least one shield member interposed between primary and secondary windings of a transformer and connected to the primary and/or secondary windings forms a distributed parasitic capacitance between the shield member and either the winding to which it is not connected or another shield member connected to that winding. Connections are made to the respective transformer windings such that the voltage distributions thus developed cause complementary common mode noise to be conducted in opposite directions in respective portions of the parasitic capacitance such that net common mode current can be made arbitrarily small without requiring that both sides of the distributed parasitic capacitance have complementary or equal voltage distributions. Such complementary common mode currents can be achieved by dividing opposing shield members or developing a voltage distribution in a single shield member in accordance with Faraday's Law.