Scholarly Works, Center for Power Electronics Systems

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https://hdl.handle.net/10919/111744

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1 kV GaN-on-Si Quasi-Vertical Schottky Rectifier
Qin, Yuan; Xiao, Ming; Zhang, Ruizhe; Xie, Qingyun; Palacios, Tomás; Wang, Boyan; Ma, Yunwei; Kravchenko, Ivan; Briggs, Dayrl P.; Hensley, Dale K.; Srijanto, Bernadeta R.; Zhang, Yuhao (IEEE, 2023-07)
This work demonstrates quasi-vertical GaN Schottky barrier diodes (SBDs) on 6-inch Si substrate with a breakdown voltage (BV) over 1 kV, the highest BV reported in vertical GaN-on-Si SBDs to date. The deep mesa inherently in quasi-vertical devices is leveraged to form a self-aligned edge termination, and the mesa sidewall is covered by the p-type nickel oxide (NiO) as a reduced surface field (RESURF) structure. This novel termination enables a parallel-plane junction electric field of 2.8 MV/cm. The device also shows low turn-on voltage of 0.5 V, and low specific on-resistance of 1.1 m ·cm2. Moreover, the device exhibits excellent overvoltage robustness under the continuous 800 V stress in the unclamped inductive switching test. These results show the good promise of the low-cost vertical GaN-on-Si power diodes.
1 kV Self-Aligned Vertical GaN Superjunction Diode
Ma, Yunwei; Porter, Matthew; Qin, Yuan; Spencer, Joseph; Du, Zhonghao; Xiao, Ming; Wang, Yifan; Kravchenko, Ivan; Briggs, Dayrl P.; Hensley, Dale K.; Udrea, Florin; Tadjer, Marko; Wang, Han; Zhang, Yuhao (IEEE, 2024-01)
This work demonstrates vertical GaN superjunction (SJ) diodes fabricated via a novel self-aligned process. The SJ comprises n-GaN pillars wrapped by the charge-balanced p-type nickel oxide (NiO). After the NiO sputtering around GaN pillars, the self-aligned process exposes the top pillar surfaces without the need for additional lithography or a patterned NiO etching which is usually difficult. The GaN SJ diode shows a breakdown voltage (B V) of 1100 V, a specific on-resistance ( RON) of 0.4 mΩ⋅ cm2, and a SJ drift-region resistance ( Rdr) of 0.13 mΩ⋅ cm2. The device also exhibits good thermal stability with B V retained over 1 kV and RON dropped to 0.3 mΩ⋅ cm2 at 125oC . The trade-off between B V and Rdr is superior to the 1D GaN limit. These results show the promise of vertical GaN SJ power devices. The self-aligned process is applicable for fabricating the heterogeneous SJ based on various wide- and ultra-wide bandgap semiconductors.
10-kV Ga₂O₃ Charge-Balance Schottky Rectifier Operational at 200 ^◦C
Qin, Yuan; Xiao, Ming; Porter, Matthew; Ma, Yunwei; Spencer, Joseph; Du, Zhonghao; Jacobs, Alan G.; Sasaki, Kohei; Wang, Han; Tadjer, Marko; Zhang, Yuhao (IEEE, 2023-08)
This work demonstrates a lateral Ga2O3 Schottky barrier diode (SBD) with a breakdown voltage (BV) over 10 kV, the highest BV reported in Ga2O3 devices to date. The 10 kV SBD shows good thermal stability up to 200◦C, which is among the highest operational temperatures reported in multi-kilovolt Ga2O3 devices. The key device design for achieving such high BV is a reduced surface field (RESURF) structure based on the p-type nickel oxide (NiO), which balances the depletion charges in the n-Ga2O3 channel at high voltage. At BV, the chargebalanced Ga2O3 SBD shows an average lateral electric field (E-field) over 4.7 MV/cm at 25 ◦C and over 3.5 MV/cm at 200◦C, both of which exceed the critical E-field of GaN and SiC. The 10 kV SBD shows a specific on-resistance of 0.27 ·cm2 and a turn-on voltage of 1 V; at 200◦C, the former doubles and the latter reduces to 0.7 V. These results suggest the good potential of Ga2O3 devices for mediumand high-voltage, high-temperature power applications.
2 kV, 0.7 mΩ·cm² Vertical Ga₂O₃ Superjunction Schottky Rectifier with Dynamic Robustness
Qin, Yuan; Porter, Matthew; Xiao, Ming; Du, Zhonghao; Zhang, Hongming; Ma, Yunwei; Spencer, Joseph; Wang, Boyan; Song, Qihao; Sasaki, Kohei; Lin, Chia-Hung; Kravchenko, Ivan; Briggs, Dayrl P.; Hensley, Dale K.; Tadjer, Marko; Wang, Han; Zhang, Yuhao (IEEE, 2023)
We report the first experimental demonstration of a vertical superjunction device in ultra-wide bandgap (UWBG) Ga2O3. The device features 1.8 μm wide, 2×1017 cm-3 doped n-Ga2O3 pillars wrapped by the charge-balanced p-type nickel oxide (NiO). The sidewall NiO is sputtered through a novel self-align process. Benefitted from the high doping in Ga2O3, the superjunction Schottky barrier diode (SJ-SBD) achieves a ultra-low specific on-resistance (RON,SP) of 0.7 mΩ·cm2 with a low turn-on voltage of 1 V and high breakdown voltage (BV) of 2000 V. The RON,SP~BV trade-off is among the best in all WBG and UWBG power SBDs. The device also shows good thermal stability with BV > 1.8 kV at 175 oC. In the unclamped inductive switching tests, the device shows a dynamic BV of 2.2 kV and no degradation under 1.7 kV repetitive switching, verifying the fast acceptor depletion in NiO under dynamic switching. Such high-temperature and switching robustness are reported for the first time in a heterogeneous superjunction. These results show the great potential of UWBG superjunction power devices.
Anti-islanding detection for three-phase distributed generation
(United States Patent and Trademark Office, 2017-04-25)
Wobbling the operating frequency of a phase-locked loop (PLL), preferably by adding a periodic variation is feedback gain or delay in reference signal phase allows the avoidance of any non-detection zone that might occur due to exact synchronization of the phase locked loop operating frequency with a reference signal. If the change in PLL operating frequency is periodic, it can be made of adequate speed variation to accommodate and time requirement for islanding detection or the like when a reference signal being tracked by the PLL is lost. Such wobbling of the PLL operating frequency is preferably achieved by addition a periodic variable gain in a feedback loop and/or adding a periodically varying phase delay in a reference signal and/or PLL output.
Artificial Neuronal Devices Based on Emerging Materials: Neuronal Dynamics and Applications
Liu, Hefei; Qin, Yuan; Chen, Hung-Yu; Wu, Jiangbin; Ma, Jiahui; Du, Zhonghao; Wang, Nan; Zou, Jingyi; Lin, Sen; Zhang, Xu; Zhang, Yuhao; Wang, Han (Wiley-V C H Verlag, 2023-03)
Artificial neuronal devices are critical building blocks of neuromorphic computing systems and currently the subject of intense research motivated by application needs from new computing technology and more realistic brain emulation. Researchers have proposed a range of device concepts that can mimic neuronal dynamics and functions. Although the switching physics and device structures of these artificial neurons are largely different, their behaviors can be described by several neuron models in a more unified manner. In this paper, the reports of artificial neuronal devices based on emerging volatile switching materials are reviewed from the perspective of the demonstrated neuron models, with a focus on the neuronal functions implemented in these devices and the exploitation of these functions for computational and sensing applications. Furthermore, the neuroscience inspirations and engineering methods to enrich the neuronal dynamics that remain to be implemented in artificial neuronal devices and networks toward realizing the full functionalities of biological neurons are discussed.
Avoiding internal switching loss in soft switching cascode structure device
(United States Patent and Trademark Office, 2017-08-15)
In a cascode switching device, avalanche breakdown of a control transistor and loss of soft switching or zero voltage switching in a high voltage normally-on depletion mode transistor having a negative switching threshold voltage and the corresponding losses are avoided by providing additional capacitance in parallel with a parallel connection of drain-source parasitic capacitance of the control transistor and gate-source parasitic capacitance of the high voltage, normally-on transistor to form a capacitive voltage divider with the drain-source parasitic capacitance of the high voltage, normally-on transistor such that the avalanche breakdown voltage of the control transistor cannot be reached. The increased capacitance also assures that the drain source parasitic capacitance of the high voltage, normally-on transistor is fully discharged before internal turn-on can occur.
Colossal tunability in high frequency magnetoelectric voltage tunable inductors
Yan, Yongke; Geng, Liwei D.; Tan, Yaohua; Ma, Jianhua; Zhang, Lujie; Sanghadasa, Mohan; Ngo, Khai D. T.; Ghosh, Avik W.; Wang, Yu U.; Priya, Shashank (2018-11-27)
The electrical modulation of magnetization through the magnetoelectric effect provides a great opportunity for developing a new generation of tunable electrical components. Magnetoelectric voltage tunable inductors (VTIs) are designed to maximize the electric field control of permeability. In order to meet the need for power electronics, VTIs operating at high frequency with large tunability and low loss are required. Here we demonstrate magnetoelectric VTIs that exhibit remarkable high inductance tunability of over 750% up to 10 MHz, completely covering the frequency range of state-of-the-art power electronics. This breakthrough is achieved based on a concept of magnetocrystalline anisotropy (MCA) cancellation, predicted in a solid solution of nickel ferrite and cobalt ferrite through first-principles calculations. Phase field model simulations are employed to observe the domain-level strain-mediated coupling between magnetization and polarization. The model reveals small MCA facilitates the magnetic domain rotation, resulting in larger permeability sensitivity and inductance tunability.
Correlation between tunability and anisotropy in magnetoelectric voltage tunable inductor (VTI)
Yan, Yongke; Geng, Liwei D.; Zhang, Lujie; Gao, Xiangyu; Gollapudi, Sreenivasulu; Song, Hyun-Cheol; Dong, Shuxiang; Sanghadasa, Mohan; Ngo, Khai D. T.; Wang, Yu U.; Priya, Shashank (Springer Nature, 2017-11-22)
Electric field modulation of magnetic properties via magnetoelectric coupling in composite materials is of fundamental and technological importance for realizing tunable energy efficient electronics. Here we provide foundational analysis on magnetoelectric voltage tunable inductor (VTI) that exhibits extremely large inductance tunability of up to 1150% under moderate electric fields. This field dependence of inductance arises from the change of permeability, which correlates with the stress dependence of magnetic anisotropy. Through combination of analytical models that were validated by experimental results, comprehensive understanding of various anisotropies on the tunability of VTI is provided. Results indicate that inclusion of magnetic materials with low magnetocrystalline anisotropy is one of the most effective ways to achieve high VTI tunability. This study opens pathway towards design of tunable circuit components that exhibit field-dependent electronic behavior.
Design of a 10 kV SiC MOSFET-based high-density, high-efficiency, modular medium-voltage power converter
Mocevic, Slavko; Yu, Jianghui; Fan, Boran; Sun, Keyao; Xu, Yue; Stewart, Joshua; Rong, Yu; Song, He; Mitrovic, Vladimir; Yan, Ning; Wang, Jun; Cvetkovic, Igor; Burgos, Rolando; Boroyevich, Dushan; DiMarino, Christina; Dong, Dong; Motwani, Jayesh Kumar; Zhang, Richard (IEEE, 2022-03)
Simultaneously imposed challenges of high-voltage insulation, high dv/dt, high-switching frequency, fast protection, and thermal management associated with the adoption of 10 kV SiC MOSFET, often pose nearly insurmountable barriers to potential users, undoubtedly hindering their penetration in medium-voltage (MV) power conversion. Key novel technologies such as enhanced gatedriver, auxiliary power supply network, PCB planar dc-bus, and high-density inductor are presented, enabling the SiC-based designs in modular MV converters, overcoming aforementioned challenges. However, purely substituting SiC design instead of Sibased ones in modular MV converters, would expectedly yield only limited gains. Therefore, to further elevate SiC-based designs, novel high-bandwidth control strategies such as switching-cycle control (SCC) and integrated capacitor-blocked transistor (ICBT), as well as high-performance/high-bandwidth communication network are developed. All these technologies combined, overcome barriers posed by state-of-the-art Si designs and unlock system level benefits such as very high power density, high-efficiency, fast dynamic response, unrestricted line frequency operation, and improved power quality, all demonstrated throughout this paper.
A diffusion-viscous analysis and experimental verification of defect formation in sintered silver bond-line
Xiao, Kewei; Ngo, Khai D. T.; Lu, Guo-Quan (Cambridge University Press, 2014-04-01)
The low-temperature joining technique (LTJT) by silver sintering is being implemented by major manufacturers of power electronic devices and modules for bonding power semiconductor chips. A common die-attach material used with LTJT is a silver paste consisting of silver powder (micrometer- or nanometer-sized particles) mixed in organic solvent and binder formulation. It is believed that the drying of the paste during the bonding process plays a critical role in determining the quality of the sintered bond-line. In this study, a model based on the diffusion of solvent molecules and viscous mechanics of the paste was introduced to determine the stress and strain states of the silver bond-line. A numerical simulation algorithm of the model was developed and coded in the C++ programming language. The numerical simulation allows determination of the time-dependent physical properties of the silver bond-line as the paste is being dried with a heating profile. The properties studied were solvent concentration, weight loss, shrinkage, stress, and strain. The stress is the cause of cracks in the bond-line and bond-line delamination. The simulated results were verified by experiments in which the formation of bond-line cracks and interface delamination was observed during the pressure-free drying of a die-attach nanosilver paste. The simulated results were consistent with our earlier experimental findings that the use of uniaxial pressure of a few mega-Pascals during the drying stage of a nanosilver paste was sufficient to produce high-quality sintered joints. The insight offered by this modeling study can be used to develop new paste formulations that enable pressure-free, low-temperature sintering of the die-attach material to significantly lower the cost of implementing the LTJT in manufacturing.
Dynamic R_ON Free 1.2 kV Vertical GaN JFET
Yang, Xin; Zhang, Ruizhe; Wang, Bixuan; Song, Qihao; Walker, Andy; Pidaparthi, Subhash; Drowley, Cliff; Zhang, Yuhao (IEEE, 2024)
Dynamic on-resistance (RON) or threshold voltage (VTH) instability caused by charge trapping is one of the most crucial reliability concerns of some GaN high-electron mobility transistors (HEMTs). It has been unclear if this issue can be resolved using an alternative GaN device architecture. This work answers this question by characterizing, for the first time, the dynamic RON and VTH stability of an industrial vertical GaN transistor-NexGen’s 1200V/70mΩ fin-channel JFET, fabricated on 100 mm bulk GaN substrates. A circuit setup is deployed for the in-situ measurement of the dynamic RON under steady-state switching. The longer-term stability of RON and VTH is tested under the prolonged stress of negative gate bias and high drain bias. The vertical GaN JFET shows nearly no RON or VTH shift in these tests, which could be attributed to the low defect density of the GaN-on-GaN homoepitaxial growth, the absence of electric field crowding near the surface, and the minimal charge trapping in the native junction gate. These results present a critical milestone for vertical GaN devices towards power electronics applications.
Dynamic Gate Breakdown of p-Gate GaN HEMTs in Inductive Power Switching
Wang, Bixuan; Zhang, Ruizhe; Wang, Hengyu; He, Quanbo; Song, Qihao; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2023-02)
We employ a new circuit method to characterize the gate dynamic breakdown voltage (BVdyn) of Schottky-type p-gate GaN HEMTs in power converters. Different from prior pulse I-V and DC stress tests, this method features a resonance-like gate ringing with the pulse width down to 20 ns and an inductive switching concurrently in the drain-source loop. At the increased pulse width, the gate BVdyn shows a decrease and then saturation at 21~22 V. Moreover, the gate BVdyn increases with temperature and is higher under the hard switching than that under the drain-source grounding condition. In the 400 V hard switching at 150 oC, the gate BVdyn reaches 27.5 V. Such impact of the drain switching locus and temperature on the gate BVdyn is not seen in Si and SiC power transistors tested in the same setup. These results are explained by a physics model that accounts for the electrostatics in the p-GaN gate stack in hard switching and at high temperatures. This work unveils new physics critical to the gate robustness of p-gate GaN HEMTs and manifest the necessity of the gate robustness evaluation in inductive switching conditions.
Energy storage for power factor correction in battery charger for electric-powered vehicles
(United States Patent and Trademark Office, 2018-03-13)
Switches of a switching circuit used to control operation of an electric motor such as in an electrically powered vehicle connect respective windings of the electric motor as a single phase inductor during battery charging. The inductor can then store inherent low frequency, second order ripple power and return that power to a load presented by a battery during battery charging to deliver substantially constant current. Storage of ripple power in the inductor allows the capacitance value, size, weight and cost of a filter capacitor of a power factor correction circuit providing input power to a battery charger to be reduced by an order of magnitude or more. Direction of current flow through the inductor is periodically reversed to avoid magnetizing the motor.
External ramp autotuning for current mode control of switching converter
(United States Patent and Trademark Office, 2017-06-13)
Peak current, valley current or average current mode controlled power converters in either digital or analog implementations obtain a stabilized feedback loop and allow high system bandwidth design by use of an external ramp generator using a slope computation equation or design parameters based on fixing the quality factor of a double pole at one-half of the switching frequency at a desired value The slope of the external ramp waveform is tuned automatically with knowledge of the slope change in the waveform of inductor current of a power converter derived by differentiating a waveform in the current feedback loop. This autotuning of the external ramp generator provides immunity of quality factor change under variations of duty cycle, component values of topological change of the power converter.
Gate Lifetime of P-Gate GaN HEMT in Inductive Power Switching
Wang, Bixuan; Zhang, Ruizhe; Wang, Hengyu; He, Quanbo; Song, Qihao; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2023-06)
The small gate overvoltage margin is a crucial concern in applications of GaN Schottky-type p-gate high electron mobility transistors (SP-HEMTs). The parasitic inductance of the gate loop can induce repetitive gate-voltage (VG) spikes during the device turn-on transients. However, the gate lifetime of the GaN SP-HEMTs under VG overshoot in power converters still remains unclear. We fill this gap by developing a new circuit method to measure the gate switching lifetime. The method features several capabilities: 1) LC-resonance-like VG overshoots with pulse width down to 20 ns and dVG/dt up to 2 V/ns; 2) adjustable power loop condition including the drain-source grounded (DSG) as well as the hard switching (HSW); and 3) repetitive switching test at an adjustable switching frequency (fSW). We use this method to test over 150 devices, and found that the gate lifetimes under a certain peak magnitude of VG overshoot (VG(PK)) can be fitted by both Weibull and Lognormal distributions. The gate lifetime is primarily determined by the number of switching cycles and is higher under the HSW than under the DSG conditions. Finally, the max VG(PK) for 10-year gate lifetime is predicted under different fSW in both DSG and HSW conditions. The results provide direct reference for GaN SP-HEMT’s converter applications and a new method for the device gate qualification.
Gate Robustness and Reliability of P-Gate GaN HEMT Evaluated by a Circuit Method
Wang, Bixuan; Zhang, Ruizhe; Song, Qihao; Wang, Hengyu; He, Quanbo; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2024-01)
The small gate overvoltage margin is a key reliability concern of the GaN Schottky-type p-gate high electron mobility transistor (GaN SP-HEMT). Current evaluation of gate reliability in GaN SP-HEMTs relies on either the DC bias stress or pulse I-V method, neither of which resembles the gate voltage (VGS) overshoot waveform in practical converters. This work develops a new circuit method to characterize the gate robustness and reliability in GaN SP-HEMTs, which features a resonance-like VGS ringing with pulse width down to 20 ns and an inductive switching concurrently in the drain-source loop. Using this method, the gate's single-pulse failure boundary, i.e., dynamic gate breakdown voltage (BVDYN), is first obtained under the hard switching (HSW) and drain-source grounded (DSG) conditions. The gate's switching lifetime is then tested under the repetitive VGS ringing, and the number of switching cycles to failure (SCTF#) is fitted by Weibull or Lognormal distributions. The SCTF# shows a power law relation with the VGS peak value and little dependence on the switching frequency. More interestingly, the gate's BVDYN and lifetime are both higher in HSW than those in DSG, as well as at higher temperatures. Such findings, as well as the gate degradation behaviors in a prolonged overvoltage stress test, can be explained by the time-dependent Schottky breakdown mechanism. The gate leakage current is found to be the major precursor of gate degradation. At 125 oC and 100 kHz, the VGS limits for a 10-year lifetime are projected to be ∼6 V and ∼10 V under the DSG and HSW conditions, respectively. These results provide a new qualification method and reveal new physical insights for gate reliability and robustness in p-gate GaN HEMTs.
Global Intergrid for Sustainable Energy Abundance
Boroyevich, Dushan; Cvetkovic, Igor; Dong, Dong (IEEE Power Electronics Society, 2022-06-04)
Invited Poster for Session on Brainstorming for Game-Changing Ideas.
High frequency integrated point-of-load power converter with embedded inductor substrate
(United States Patent and Trademark Office, 2017-02-07)
A low profile power converter structure is provide wherein volume is reduced and power density is increased to approach 1 KW/in3 by at least one of forming an inductor as a body of magnetic material embedded in a substrate formed by a plurality of printed circuit board (PCB) lamina and forming inductor windings of PCB cladding and vias which may be of any desired number of turns and may include inversely coupled windings and which provide a lateral flux path, forming the body of magnetic material from high aspect ratio flakes of magnetic material which are aligned with the inductor magnetic field in an insulating organic binder and hot-pressed and providing a four-layer architecture comprising two layers of PCB lamina including the embedded body of magnetic material, a shield layer and an additional layer of PCB lamina, including cladding for supporting and connecting a switching circuit, a capacitor and the inductor.
Hybrid interleaving structure with adaptive phase locked loop for variable frequency controlled switching converter
(United States Patent and Trademark Office, 2018-07-03)
In a multi-phase power converter using a phase-locked loop (PLL) arrangement for interleaving of pulse frequency modulated (PFM) pulses of the respective phases, improved transient response, improved stability of high bandwidth output voltage feedback loop, guaranteed stability of the PLL loop and avoidance of jittering and phase cancellation issues are achieved by anchoring the bandwidth at the frequency of peak phase margin. This methodology is applicable to multi-phase power conveners of any number of phases and any known or foreseeable topology for individual phases and is not only applicable to power converters operating under constant on-time control, but is extendable to ramp pulse modulation (RPM) control and hysteresis control. Interleaving of pulses from all phases is simplified through use of phase managers with a reduced number of PLLS using hybrid interleaving arrangements that do not exhibit jittering even when ripple is completely canceled.

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