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    A Device-Level FPGA Simulator

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    Jesse_Hunter-Thesis.pdf (6.663Mb)
    Downloads: 843
    Date
    2000-04-07
    Author
    Hunter, Jesse Everett III
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    Abstract
    In the realm of FPGAs, many tool vendors offer behaviorally-based simulators aimed at easing the complexity of large FPGA designs. At times, a behaviorally-modeled design does not work in hardware as expected or intended. VTsim, a Virtex-II device simulator, was designed to resolve this and many other design problems by providing a window into the FPGA fabric via a virtual device. VTsim is an event-driven device simulator modeled at the CLB level with multiple clock domain support. Utilizing JBits3 and ADB, VTsim enables simulation and examination of all resources within an FPGA via a virtual device. The only input required by VTsim is a bitstream, which can be generated from any tool suite. The simulator is part of the JHDLBits open-source project, and was designed for rapid response, low memory usage, and ease of interaction.
    URI
    http://hdl.handle.net/10919/10041
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    • Masters Theses [21567]

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