A Reliable CMOS Receiver for Power Line Communications in Integrated Circuits

Power line communications (PLC) in integrated circuits (ICs) was proposed by Dr. Dong S. Ha's group in 2005. Their goal was to utilize the power distribution network for data communications as well as delivery of power, so that the routing overhead can be avoided and the number of pins in the chip can be reduced. Dr. Ha's group demonstrated through measurements the existence of pass-bands in the power distribution networks and the feasibility of power line communications in ICs. Several PLC receivers were developed to recover data superimposed on the power lines of an IC. This thesis research investigated a new PLC receiver to improve shortcomings of previous PLC receivers, specifically to improve the reliability while reducing power dissipation.

The proposed PLC system adopts an amplitude shift keying (ASK) modulation to transmit and detect data through power distribution networks. The proposed PLC receiver consists of three main sub-blocks. The first sub-block is a level shifter, which lowers the offset voltage of the supply voltage to approximately 0.5VDD. The second sub-block is a signal extractor, which detects a data signal superimposed on the power line. The signal extractor is a differential amplifier, in which one input is connected through an RC low-pass filter. The DC voltage of the data signal varies in accordance with the supply voltage fluctuations and droop. The low-pass filter intends to pass only the DC term of the data signal. Since the DC voltage is common for both inputs of the differential amplifier, it is removed from the data signal through the common mode rejection of the differential amplifier. Therefore, the signal extractor can mitigate supply voltage fluctuations and droops. The last sub-block is the logic restorer, which converts the differential signal to a logic value based on a Schmitt trigger. The hysteresis of the Schmitt trigger improves the noise immunity of the receiver

The proposed PLC receiver is designed and fabricated in CMOS 0.18 µm technology under the supply voltage of 1.8 V. Measurement results of the three sub-blocks and the entire PLC receiver are presented and compared with simulation results. The data rate for the measurements is set to 10.0 Mbps, and the ASK modulation scheme adopts VDD (= 1.8 V) for logic 0 and 90 mV above VDD for logic 1. The measurements show that the PLC receiver can tolerate the supply voltage drop by 0.423 V or 23.0%. The power dissipation for the receiver is 3.2 mW under 1.8 V supply. The core area of the receiver is 72.2 µm x 74.9 µm.