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dc.contributor.authorTavaragiri, Abhayen_US
dc.date.accessioned2011-07-21en_US
dc.date.accessioned2014-03-14T20:41:11Z
dc.date.available2011-07-21en_US
dc.date.available2014-03-14T20:41:11Z
dc.date.issued2011-07-07en_US
dc.date.submitted2011-07-07en_US
dc.identifier.otheretd-07072011-145912en_US
dc.identifier.urihttp://hdl.handle.net/10919/33923
dc.description.abstractAdvances in FPGA density and complexity have not been matched by a corresponding improvement in the performance of the implementation tools. Knowledge of incremental changes in a design can lead to fast turnaround times for implementing even large designs. A high-level overview of an incremental productivity flow, focusing on the back-end FPGA design is provided in this thesis. This thesis presents a management paradigm that is used to capture the design specific information in a format that is reusable across the entire design process. A C++ based internal data structure stores all the information, whereas XML is used to provide an external view of the design data. This work provides a vendor independent, universal format for representing the logical and physical information associated with FPGA designs.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartTavaragiri_A_T_2011.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectFPGA Management Techniqueen_US
dc.subjectXMLen_US
dc.subjectProductivityen_US
dc.subjectTORCen_US
dc.titleA Management Paradigm for FPGA Design Flow Accelerationen_US
dc.typethesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
dc.contributor.committeechairAthanas, Peter M.en_US
dc.contributor.committeememberSchaumont, Patrick Roberten_US
dc.contributor.committeememberTront, Joseph G.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-07072011-145912/en_US


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