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The use of VHDL in computer-aided support of life-cycle complete product design
Successful competition in the computer systems industry depends on a firm's ability to
bring profitable products to market. The success of a product is measured by its future
worth to the company. Life-cycle complete design attempts to engineer products that
provide maximum future worth. Many components contribute to the overall cost of
developing a product. Designing merely to reduce the cost of the components that make
up the system is insufficient.
A product must be engineered in a manner that addresses all pertinent issues over its
complete life cycle. This research examines the use of the VHSIC Hardware Description
Language as a computer-aided engineering tool for life-cycle complete engineering.
VHDL is traditionally used to model the functional behavior of digital systems. This thesis
provides an overview of a life-cycle complete design process and describes the use of
VHDL to support that process. A case study is presented to illustrate the use of VHDL
for life-cycle complete modeling.