The purpose of radar signal processing is to extract desired data from radar signals. Testing of the radar signal processor requires that one produce a test consisting of a sequence of digitized radar sensor data. If the signal processor is modeled in VHDL then the sequence of sensor data will be applied to the model in a VHDL test bench. Generation of the sensor data and sensor models for VHDL testbenches is a labor intensive task which cannot be performed manually.

This thesis concentrates on the transformation of the mathematical representations of Synthetic Aperture Radar signals and sensors into VHDL models, and provides the mathematical underpinning for the other testbench work. Cadence/Comdisco SPW is used to describe the behavioral model of the test bench, which is hierarchically constructed using the primitives in the SPW library. A parameterized VHDL model is constructed from the block diagrams in SPW to generate the test for the VHDL signal processing model under test.