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dc.contributor.authorTyagi, Dhawalen_US
dc.date.accessioned2014-03-14T21:39:26Z
dc.date.available2014-03-14T21:39:26Z
dc.date.issued1994en_US
dc.identifier.otheretd-06302009-040525en_US
dc.identifier.urihttp://hdl.handle.net/10919/43515
dc.format.mediumBTDen_US
dc.publisherVirginia Techen_US
dc.relation.haspartLD5655.V855_1994.T934.pdfen_US
dc.subjectIntegrated circuitsen_US
dc.subject.lccLD5655.V855 1994.T934en_US
dc.titleTENOR :an ATPG for transition faults in combinational circuitsen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical Engineeringen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-06302009-040525/en_US
dc.date.sdate2009-06-30en_US
dc.date.rdate2009-06-30
dc.date.adate2009-06-30en_US


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