Design and implementation of a reconfigurable FPGA-based video frame grabber board

This thesis describes the design and implementation of the JB1 reconfigurable video frame grabber board and its use in the Virginia Tech Splash system. The system utilizes the frame grabber board to provide the Splash-2 platform with real time digital images suitable for image processing. The board converts analog black and white video images (RS-170 format) into digital grey scale images of sizes up to 480 rows x 512 columns x 8 bits per pixel. The resulting images are then transferred to the Splash-2 platform in real time for subsequent processing. The board utilizes two Xilinx field programmable gate arrays (FPGAs) for implementation of different configurations. A software user interface has also been developed to control the operation of the board.