Vector processor services for local area networks

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1991
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Virginia Tech
Abstract

Vector processors conventionally have been used as an attached processor to a host computer. Within this limited scope, the application programmer must use the host computer in order to benefit from the vector processor resources. By using a local area network, programmers are no longer constrained to a specific host computer. The vector processor may be shared as a network resource.

The vector processor service is developed within a distributed environment and, therefore, must address concerns pertinent to distributed system architecture. These issues include implementation methodologies, interprocess communication performance, protocol processing and network throughput, and the level of transparency of the implementations. This thesis presents models that facilitate implementation of the vector processor service over a local area network (LAN). The research investigates the performance of different interprocess communication techniques and alternative transport protocols, specifically TCP and UDP. Additionally, two LAN technologies are examined for the vector processor service, namely Ethernet and Fiber Data Distributed Interface (FDDI).

Experiments are performed for a batch application using an Ethernet local area network. Simulations are done for a real-time application utilizing an Ethernet LAN as well as for the same batch application. Additionally, a FDDI local area network is simulated for a real-time application. Results indicate that the model based on remote program execution has better performance because of lower network communication overhead compared to the model based on remote procedure calls. However, the remote procedure call model provides for a more transparent implementation of the vector processor service. This thesis also discusses methods to improve the performance of the vector processor service, including better implementations and transport protocols, alternative remote procedure call protocols, and new multiprocessor architectures.

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