An investigation of sensitization conditions and test effectiveness for CMOS faults

Testing of digital circuits ensures functionality and reliability of the circuits. Previous research has addressed the inadequacies of conventional test methods based on line stuck-at faults in testing CMOS circuits and has proposed new test methods. In this research, the effectiveness of propagation delay testing for open and short faults and supply current monitoring for short faults is investigated. Representative circuits are modeled and simulated over a wide range of fault severities. Factors, such as circuit and fault features, that affect test effectiveness are evaluated and analyzed. From the results, general conclusions are drawn and future research is proposed.