Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test

Abstract

Post-Silicon validation is playing an increasingly important role as more chips are failing in the functional mode due to either manufacturing defects escaped during scan-based tests or design bugs missed during pre-silicon validation. Critical to the diagnosis engineer is the ability to observe as many relevant internal signal values as possible during debug. To do so, trace buffers have been proposed for enhancing the observability of internal signals during post-silicon debug. Trace Buffers are used to trace (record the values of) the internal signals in real-time when chip is in its normal operation. However, existing trace buffer architectures trace very few signals for a large number of cycles. Thus, even with a good subset of signals traced, one often still cannot restore all the relevant values in the circuit. In this work, we propose two different flexible trace buffer architectures that can restore the values for all signals by making the trace signals configurable. In addition, the buffer space can also be shared among different traced signals which makes the architectures highly flexible. As compared to conventional trace buffer architectures, the new architectures have comparable area overhead but offer the ability to restore all signals in the circuit. For cases of less than 100% restoration, the ability of circuit invariants to improve the signal restoration is explored. A promising direction for the future work is provided where targeted invariants may lead to better restoration scenario during post-silicon validation.