A Two-mode Buck Converter toward High Efficiency for the Entire Load Range for Low Power Applications
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In order to extend the battery life of smart cameras, it is essential to increase the efficiency of power converters, especially at light load. This thesis research investigated a power converter to supply power for the microprocessor of a smart camera. The input voltage of the converter is 5 V, and the output voltage is 1.2 V with the load ranging from 10 mA (12 mW) to 1200 mA (1440 mW). The conventional buck converter is typically optimized for high efficiency at maximum load at the cost of light-load efficiency. A converter is investigated in this thesis to improve light load efficiency, while being able to handle heavy load, to prolong the battery life of smart cameras. The proposed converter employs two modes, a baby-buck mode and a heavy-load mode, in which each mode is optimized for its respective load range to achieve high efficiency throughout entire range. The heavy-load mode converter adopts the conventional synchronous buck approach, as it generally achieves high efficiency at heavy load. However, the synchronous buck approach is inefficient at light load due to the large switching, driving, and controller losses. The proposed baby-buck mode converter employs the following schemes or technique to reduce those losses. First, the baby buck mode converter adopts pulse frequency modulation (PFM) with discontinuous conduction mode (DCM) to lower the switching frequency at light load, so frequency-dependent switching and driving losses are reduced. Second, a simple control scheme, constant on-time V2 control, is adopted to simplify the controller and hence minimize the controller power dissipation. Third, the top switch of the baby-buck mode uses a small MOSFET, which is optimized for light load, and the bottom switch uses Schottky diode in lieu of a MOSFET to simplify the COT V2 controller. Fourth, the proposed converter combines the heavy-load and baby-buck mode converter into a single converter with a shared inductor, capacitors, and the feedback controller to save space. Finally, a simple and low power feedback controller with an optimum mode selector, a COT V 2 controller, and gate drivers are designed. The optimum mode selector selects an appropriate mode based on the load condition, while shutting down the opposing mode. The proposed converter was fabricated in CMOS 0.25 µm technology in two phases. Phase 1 contains design of the proposed converter with open loop, and its functionality is verified through measurements of test chips. Phase 2 includes the entire converter design with the feedback controller. Since the test chips of phase 2 are not delivered, yet, its functionality during the steady state and transient responses are verified through simulations. Simulation results indicate that the efficiency of the proposed converter ranges from 74% to 93% at 12 mW and 1440 mW, respectively. This result demonstrates that the proposed converter can achieve higher efficiency for the entire load range when compared to an off-the-shelf synchronous buck converters.
- Masters Theses