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Hybrid Active Power Filter with Output Impedance Control
Schmit, Andrew Paul
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In an ideal world, unwanted or undesirable effects in a system could and would be completely ignored. In fact, this was the case in mid-80s' PC design when an 80286 microprocessor running at a "blazing" 12 MHz was considered leading-edge technology. As technology continued to push the envelope and ever-faster designs were realized, more demanding software packages were developed and utilized efficiently. These increasingly sophisticated software packages in turn allowed designers of all disciplines to test systems of escalating complexity. These more complex models placed a heavier burden on the hardware, prompting a push for better and faster hardware designs. The cycle repeats to this day. As such, we are now in an environment where a 1 GHz microprocessor is considered somewhat dated. More importantly, whereas a small 1 nH (1 billionth of a Henry) inductance in a power delivery path was considered inconsequential a decade ago, it is now a barrier to implementing a design. Similarly, the equivalent series inductance (ESL) of a capacitor plays an increasing (and detrimental) role in the behavior and design of today's VRM (Voltage Regulator Module) design. In fact, it is the ESL of the capacitor that hinders proper voltage regulation at high frequencies by increasing the output impedance beyond a desired level. This dilemma has been recognized and several topologies have been proposed to overcome this problem. One category is improved passive devices, with the latest involving array capacitors to achieve near-zero ESL. As passive devices are almost always preferable to active solutions due to their lower losses, these technologies hold great promise, though they are inherently limited in small-footprint applications. A second category is the addition of active devices, which involves the use of some filtering technique to inject or absorb current during a fast transient by the use of semiconductor switches connected to a power source. These switching-state topologies have been shown to be prone to unstable oscillations, often caused by over-reactions or over-corrections of one transient prompting the opposite switch to engage its power source. The research goal is to develop a methodology to use active filters to more-seamlessly extend the control bandwidth of today's VRM technology. A hybrid active power filter is developed which uses bipolar junction transistors (BJT) in the forward-active region to connect a power supply source to the microprocessor. In this way, the switches are used in a way analogous to a dimmer switch (vs. simply 'on' or 'off'). By proper design of the compensator in the feedback loop, the active power filter can be used to suppress transients in any desired frequency range, limited only by the amplifier's current rating and bandwidth. The compensator design's derivation shows the relationship to the output impedance of the active filter. In essence, we are â€˜designing' a capacitor with a very low ESL, having more desirable output impedance vs. frequency relationship than either a capacitor, or a more complicated VRM with an extended bandwidth. Using this design, however, at very high frequencies (i.e., approaching 1 GHz, or one trillion cycles per second) requires state-of-the-art packaging designs to limit unwanted impedances, and also an ultra-wide GHz bandwidth, high-current operational amplifier. Both of these barriers are outside the scope of this research. As is often the case in research efforts, we have not â€˜solved' the problem, but have shifted it to a frequency range where the effect isn't problematic. Experimental results show the use of a hybrid power filter with a VRM with Adaptive Voltage Positioning (AVP) can significantly suppress voltage undershoot during fast transient load current changes. In addition, the design is modified to reduce and possibly eliminate bulk output capacitors. This provides a promising alternative to a Voltage Regulator Module with a very high control bandwidth. Lastly, simulations give an estimate of the required IC design to use an APF to augment packaging capacitors.
- Masters Theses