An improved chip-level test generation algorithm

Abstract

An improved algorithm for the automatic generation of test vectors from chip-level descriptions written in VHDL is described. The method offers an order of magnitude speed improvement over earlier test generation algorithms. The algorithm accepts data flow circuit descriptions written in a subset of VHDL. A fault model which defines faults for the VHDL statements is applied to determine fault cases. Test generation requirements of fault sensitization, value justification, and fault effect propagation are expressed in terms of justification, propagation, and execution goals, rather than in terms of low-level operations. Prolog rules define the way in which the goals are satisfied, using backtracking to select alternative solutions. A method for handling time in absolute, rather than relative, terms is discussed. Comparison of run times for the improved algorithm against those obtained by the previous method is made to demonstrate the speedup. Suggestions for incorporating the algorithm into a test generation system are discussed. A user’s guide is given for the current implementation of the method.