An improved chip-level test generation algorithm

dc.contributor.authorO'Neill, Michael Douglasen
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:38:23Zen
dc.date.adate2010-06-12en
dc.date.available2014-03-14T21:38:23Zen
dc.date.issued1988en
dc.date.rdate2010-06-12en
dc.date.sdate2010-06-12en
dc.description.abstractAn improved algorithm for the automatic generation of test vectors from chip-level descriptions written in VHDL is described. The method offers an order of magnitude speed improvement over earlier test generation algorithms. The algorithm accepts data flow circuit descriptions written in a subset of VHDL. A fault model which defines faults for the VHDL statements is applied to determine fault cases. Test generation requirements of fault sensitization, value justification, and fault effect propagation are expressed in terms of justification, propagation, and execution goals, rather than in terms of low-level operations. Prolog rules define the way in which the goals are satisfied, using backtracking to select alternative solutions. A method for handling time in absolute, rather than relative, terms is discussed. Comparison of run times for the improved algorithm against those obtained by the previous method is made to demonstrate the speedup. Suggestions for incorporating the algorithm into a test generation system are discussed. A user’s guide is given for the current implementation of the method.en
dc.description.degreeMaster of Scienceen
dc.format.extentviii, 108 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-06122010-020415en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-06122010-020415/en
dc.identifier.urihttp://hdl.handle.net/10919/43262en
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1988.O645.pdfen
dc.relation.isformatofOCLC# 17796926en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1988.O645en
dc.subject.lcshIntegrated circuits -- Large scale integrationen
dc.titleAn improved chip-level test generation algorithmen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen
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