Parallel pipelined VLSI arrays for real-time image processing

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Virginia Polytechnic Institute and State University


Real-time image processing involves processing a wide spectrum of algorithms on huge data sets. Processing at the pixel data rate demands more powerful parallel machines than those developed for conventional image processing.

This research takes advantage of current VLSI technology to examine a new approach for processing arbitrary algorithms at real-time data rate. It is based on embedding the algorithms, expressed by their dependency graphs, into two dimensional regularly connected processing arrays. Each node in a graph represents an operation which can be processed by an individual processor in the array. The embedding is performed such that data can be processed in a pipeline fashion as they are received. The result is a machine which exploits functional parallelism and data pipelining simultaneously.

The presentation is divided into three parts: the first discusses graphical representation for general image processing algorithms, taking into account the nature of the data flow in real-time systems. The conditions for pipelining the processing of the graph are derived.

Next the logical design of a class of VLSI arrays is considered. These arrays can be configured to embed arbitrary problem graphs. The discussion involves the architecture of the array, the architecture of its processing elements and an efficient programming scheme.

Finally, static embedding of the dependency graphs into the proposed array is considered. Lower and upper bounds on the area needed to embed any graph are found. Three heuristic procedures to embed the graph at minimum cost are developed, implemented and tested.