Parallel pipelined VLSI arrays for real-time image processing

Simple item page
dc.contributor.authorAli, Faridah M.en
dc.contributor.committeechairNadler, Mortonen
dc.contributor.committeememberYu, K.B.en
dc.contributor.committeememberTront, Joseph G.en
dc.contributor.committeememberBixler, J.P.en
dc.contributor.committeememberArmstrong, James R.en
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-08-13T14:38:46Zen
dc.date.available2014-08-13T14:38:46Zen
dc.date.issued1988en
dc.description.abstractReal-time image processing involves processing a wide spectrum of algorithms on huge data sets. Processing at the pixel data rate demands more powerful parallel machines than those developed for conventional image processing. This research takes advantage of current VLSI technology to examine a new approach for processing arbitrary algorithms at real-time data rate. It is based on embedding the algorithms, expressed by their dependency graphs, into two dimensional regularly connected processing arrays. Each node in a graph represents an operation which can be processed by an individual processor in the array. The embedding is performed such that data can be processed in a pipeline fashion as they are received. The result is a machine which exploits functional parallelism and data pipelining simultaneously. The presentation is divided into three parts: the first discusses graphical representation for general image processing algorithms, taking into account the nature of the data flow in real-time systems. The conditions for pipelining the processing of the graph are derived. Next the logical design of a class of VLSI arrays is considered. These arrays can be configured to embed arbitrary problem graphs. The discussion involves the architecture of the array, the architecture of its processing elements and an efficient programming scheme. Finally, static embedding of the dependency graphs into the proposed array is considered. Lower and upper bounds on the area needed to embed any graph are found. Three heuristic procedures to embed the graph at minimum cost are developed, implemented and tested.en
dc.description.adminincomplete_metadataen
dc.description.degreePh. D.en
dc.format.extentxi, 172 leavesen
dc.format.mimetypeapplication/pdfen
dc.identifier.urihttp://hdl.handle.net/10919/49914en
dc.publisherVirginia Polytechnic Institute and State Universityen
dc.relation.isformatofOCLC# 18363769en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V856 1988.A442en
dc.subject.lcshIntegrated circuits -- Very large scale integrationen
dc.subject.lcshImage processingen
dc.titleParallel pipelined VLSI arrays for real-time image processingen
dc.typeDissertationen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.leveldoctoralen
thesis.degree.namePh. D.en

Files

Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
LD5655.V856_1988.A442.pdf
Size:
3.99 MB
Format:
Adobe Portable Document Format
Description:
Download

Collections

Doctoral Dissertations