A Behavioral Test Strategy For Board Level Systems

dc.contributor.authorHameed, Qaisaren
dc.contributor.committeechairGray, Festus Gailen
dc.contributor.committeememberHa, Dong Samen
dc.contributor.committeememberArmstrong, James R.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:32:30Zen
dc.date.adate1999-03-13en
dc.date.available2014-03-14T20:32:30Zen
dc.date.issued1999-03-03en
dc.date.rdate1999-03-13en
dc.date.sdate1999-03-10en
dc.description.abstractA digital board typically contains a heterogeneous mixture of chips: microprocessors, memory, control and I/O logic. Different testing techniques are needed for each of these components. To test the whole board, these techniques must be integrated into an overall testing strategy for the board. In this thesis, we have applied a behavioral testing scheme to test the board. Each component chip is tested by observing the behavior of the system in response to the test code, i.e. the component under test is not isolated from the rest of the circuit during test. This obviates the need for the extra hardware used for isolating the chips that is required for structural testing. But this is done at the cost of reduced fault location, although fault detection is still adequate. We have applied the start small approach to behavioral testing. We start by testing a small core of functions. Then, only those functions already tested are used to test the remaining behavior. The grand goal is testing the whole board. This is divided into goals for testing each of the individual chips, which is further subdivided into sub-goals for each of the sub-functions of the board or sub-goals for testing for the most common faults in a component. Each component is tested one by one. Once a component passes, it is put in a passed items set and then can be used in testing the remaining components. Using the start small approach helps isolate the faults to the chip level and thus results in better fault location than the simple behavioral testing scheme in which there is no concept of passed items set and its usage. As an example, this testing approach is applied to a microcontroller based temperature sensor board. This code is run on the VHDL model of the system, and then also on the actual system. For modeling the system in VHDL, Synopsys Smart model library components are used. Faults are injected in the system and then the performance of the strategy is evaluated. This strategy is found to be very effective in detecting internal faults of the chip and locating the faults to the chip level. The interconnection faults are difficult to locate although they are detected in most of the cases. Different scenarios for incorporating this scheme in legacy systems are also discussed.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-031099-213422en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-031099-213422/en
dc.identifier.urihttp://hdl.handle.net/10919/31445en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartintrochap1.pdfen
dc.relation.haspartchap4.pdfen
dc.relation.haspartchap2.pdfen
dc.relation.haspartappendix.pdfen
dc.relation.haspartchap3.pdfen
dc.relation.haspartchap5nref.pdfen
dc.relation.haspartvita.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectMarch Xen
dc.subjectSmart Modelen
dc.subjectStart Smallen
dc.subjectVHDLen
dc.subjectAssemblyen
dc.subjectLegacy Systemsen
dc.subjectTestingen
dc.titleA Behavioral Test Strategy For Board Level Systemsen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen
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