A Two-Phase Buck Converter with Optimum Phase Selection for Low Power Applications
Power consumption of smart cameras varies significantly between sleep mode and active mode, and a smart camera operates in sleep mode for 80 — 90% of time for typical use. To prolong the battery life of smart cameras, it is essential to increase the power converter efficiency for light load, while being able to manage heavy load. The power stage of traditional buck converter is optimized for maximum load, at the cost of light-load efficiency. Wei proposed a multiphase buck converter incorporating the baby-buck concept and optimum number of phases (ONP) control. This thesis research investigated Wei's multiphase buck converter to improve the light-load efficiency for smart cameras as the target application.
The proposed two-phase buck converter aims to provide power for microprocessors of smart cameras. The input voltage of the converter is 5 V DC, and the output voltage is 1.2 V DC with power dissipation range of 25 mA (30 mW) for light load and 833 mA (1 W) for heavy load. Three methods are considered to improve light-load efficiency: adopting baby-buck concept, adapting ONP control for low-power range, and implementing a pulse frequency modulation (PFM) control scheme with discontinuous conduction mode (DCM) to lower switching frequency. The first method is to adopt the baby-buck concept through power stage design of each phase to optimize efficiency for a specific load range. The baby-buck phase is optimized for light load and the heavy-load phase is designed to handle the processors maximum power consumption. The second method performs phase selection from sensed load current information. Rather than have all phases active for heavy-load as in ONP control, optimum phase selection (OPS) control is introduced to adaptively select between phases based on load current. Due to low-power constraints, OPS is more efficient for the medium to heavy-load range. The transition between phases due to load change is also investigated. The third and final method implements PFM control with DCM to lower switching frequency and reduce switching and driving losses under light load. PFM is accomplished with a constant on-time (COT) valley current mode controller, which uses the inductor current information and output voltage to generate switching signals for both the top and bottom switches. The baby-buck phase enters DCM to lower switching frequency under very light load, while the heavy-load phase remains in continuous conduction mode (CCM) throughout its load range.
The proposed two-phase buck converter is designed and prototyped using discrete components. Efficiency of the two-phase converter and a power loss breakdown for each block in the control scheme were measured. The efficiency ranges from 64% to 81% for light load ranging of 30 mW to 200 mW, and the efficiency ranges from 81% to 88% for heavy load ranging from 200 mW to 1 W. The majority loss is due to controllers, which are responsible for 37 % (8.6 mW) for light load of 60 mW and for 10.9 % (9 mW) for heavy load of 600 mW. The gate driver loss is considerable for heavy load of 600 mW, consuming 11.9% (9.8mW). The converter has a 10 mV overshoot voltage for a load step-down from 225 mA to 25 mA, and it has 65 mV overshoot voltage for a load step-up from 25 mA to 225 mA. Although, a fair comparison is difficult due to use of discrete parts for OPS control, the proposed converter shows reasonably good efficiency and performance.