Graphics Processors for an HDL Simulator
| dc.contributor.author | Kandappan, Parthiban | en |
| dc.contributor.department | Electrical Engineering | en |
| dc.date.accessioned | 2021-10-26T20:10:10Z | en |
| dc.date.available | 2021-10-26T20:10:10Z | en |
| dc.date.issued | 1986 | en |
| dc.description.abstract | A new CAD tool, aimed at providing a simple graphical interface to the chip-level simulation system GSP, has been developed. It consists of pre and post-processors allowing the user to model systems using pre-defined library as well as custom modules and to view their outputs in a more familiar waveform-like display. The actual coding of the models is still the responsibility of the user; the pre-processor enables the net list specification as well as the input of simulator commands in a menu-based approach. Facilities for simple data checking as well as hardcopy generation of system models has been provided. Developed to run on the IBM PC, this system also integrates the three discrete parts of GSP, viz. GSPASM, GSPLINK and GSPSIM along with the graphics processors into a single menu-based system. | en |
| dc.description.degree | M.S. | en |
| dc.format.extent | vii, 78 leaves | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.uri | http://hdl.handle.net/10919/106112 | en |
| dc.language.iso | en | en |
| dc.publisher | Virginia Polytechnic Institute and State University | en |
| dc.relation.isformatof | OCLC# 15183049 | en |
| dc.rights | In Copyright | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject.lcc | LD5655.V855 1986.K374 | en |
| dc.subject.lcsh | Logic circuits | en |
| dc.title | Graphics Processors for an HDL Simulator | en |
| dc.type | Thesis | en |
| dc.type.dcmitype | Text | en |
| thesis.degree.discipline | Electrical Engineering | en |
| thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
| thesis.degree.level | masters | en |
| thesis.degree.name | M.S. | en |
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