Gigahertz-Range Multiplier Architectures Using MOS Current Mode Logic (MCML)

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dc.contributor.authorSrinivasan, Venkataramanujamen
dc.contributor.committeechairHa, Dong Samen
dc.contributor.committeememberArmstrong, James R.en
dc.contributor.committeememberTront, Joseph G.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2011-08-06T14:43:26Zen
dc.date.adate2003-12-18en
dc.date.available2011-08-06T14:43:26Zen
dc.date.issued2003-12-05en
dc.date.rdate2004-12-18en
dc.date.sdate2003-12-05en
dc.description.abstractThe tremendous advancement in VLSI technologies in the past decade has fueled the need for intricate tradeoffs among speed, power dissipation and area. With gigahertz range microprocessors becoming commonplace, it is a typical design requirement to push the speed to its extreme while minimizing power dissipation and die area. Multipliers are critical components of many computational intensive circuits such as real time signal processing and arithmetic systems. The increasing demand in speed for floating-point co-processors, graphic processing units, CDMA systems and DSP chips has shaped the need for high-speed multipliers. The focus of our research for modern digital systems is two fold. The first one is to analyze a relatively unexplored logic style called MOS Current Mode Logic (MCML), which is a promising logic technique for the design of high performance arithmetic circuits with minimal power dissipation. The second one is to design high-speed arithmetic circuits, in particular, gigahertz-range multipliers that exploit the many attractive features of the MCML logic style. A small library of MCML gates that form the core components of the multiplier were designed and optimized for high-speed operation. The three 8-bit MCML multiplier architectures designed and simulated in TSMC 0.18 mm CMOS technology are: 3-2-tree architecture with ripple carry adder (Architecture I), 4-2-tree design with ripple carry adder (Architecture II) and 4-2-tree architecture with carry look-ahead adders (Architecture III). Architecture I operates with a maximum throughput of 4.76 GHz (4.76 Billion multiplications per second) and a latency of 3.78 ns. Architecture II has a maximum throughput of 3.3 GHz and a latency of 3 ns and Architecture III has a maximum throughput of 2 GHz and a latency of 3 ns. Architecture I achieves the highest throughput among the three multipliers, but it incurs the largest area and latency, in terms of clock cycle count as well as absolute delay. Although it is difficult to compare the speed of our multipliers with existing ones, due to the use of different technologies and different optimization goals, we believe our multipliers are among the fastest found in contemporary literature.en
dc.description.degreeMaster of Scienceen
dc.format.mediumETDen
dc.identifier.otheretd-12052003-112258en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-12052003-112258en
dc.identifier.urihttp://hdl.handle.net/10919/9643en
dc.publisherVirginia Techen
dc.relation.haspartChapters1_6.pdfen
dc.relation.haspartContents.pdfen
dc.relation.haspartTitle_Abstract.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectVLSI designen
dc.subjectMCMLen
dc.subjectHigh-speed circuit designen
dc.subjectHigh-speed multipliersen
dc.titleGigahertz-Range Multiplier Architectures Using MOS Current Mode Logic (MCML)en
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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