Design of a digital logic trainer
| dc.contributor.author | Allen, James Dillino | en |
| dc.contributor.department | Electrical Engineering | en |
| dc.date.accessioned | 2017-01-30T21:03:16Z | en |
| dc.date.available | 2017-01-30T21:03:16Z | en |
| dc.date.issued | 1965 | en |
| dc.description.abstract | In this thesis a binary digital system, capable of performing arithmetic operations, was developed from a simple two-state (binary digital) device. This binary digital system or digital computer could be programmed to add, subtract or multiply and perform many other logic functions. The above operations are performed serially in seven bit shift registers. The system is manually programmed using an Instruction Select Switch. During each phase of the development of the system, an example of the procedure used to reach a conclusion during that phase was explained at length. It is hoped that following and continually reapplying the basic procedures outlined in this thesis, particularly in the development of the Full Adder, would allow for the design of any moderately complex digital system. | en |
| dc.description.degree | Master of Science | en |
| dc.format.extent | iv, 60 leaves | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.uri | http://hdl.handle.net/10919/74587 | en |
| dc.language.iso | en_US | en |
| dc.publisher | Virginia Polytechnic Institute | en |
| dc.relation.isformatof | OCLC# 20661515 | en |
| dc.rights | In Copyright | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject.lcc | LD5655.V855 1965.A442 | en |
| dc.subject.lcsh | Electronic digital computers -- Design and construction | en |
| dc.title | Design of a digital logic trainer | en |
| dc.type | Thesis | en |
| dc.type.dcmitype | Text | en |
| thesis.degree.discipline | Electrical Engineering | en |
| thesis.degree.grantor | Virginia Polytechnic Institute | en |
| thesis.degree.level | masters | en |
| thesis.degree.name | Master of Science | en |
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