Towards Using Free Memory to Improve Microarchitecture Performance
dc.contributor.author | Panwar, Gagandeep | en |
dc.contributor.committeechair | Ravindran, Binoy | en |
dc.contributor.committeecochair | Jian, Xun | en |
dc.contributor.committeemember | Patterson, Cameron D. | en |
dc.contributor.department | Electrical and Computer Engineering | en |
dc.date.accessioned | 2020-06-04T15:54:42Z | en |
dc.date.available | 2020-06-04T15:54:42Z | en |
dc.date.issued | 2020-05-18 | en |
dc.description.abstract | A computer system's memory is designed to accommodate the worst-case workloads with the highest memory requirement; as such, memory is underutilized when a system runs workloads with common-case memory requirements. Through a large-scale study of four production HPC systems, we find that memory underutilization problem in HPC systems is very severe. As unused memory is wasted memory, we propose exposing a compute node's unused memory to its CPU(s) through a user-transparent CPU-OS codesign. This can enable many new microarchitecture techniques that transparently leverage unused memory locations to help improve microarchitecture performance. We refer to these techniques as Free-memory-aware Microarchitecture Techniques (FMTs). In the context of HPC systems, we present a detailed example of an FMT called Free-memory-aware Replication (FMR). FMR replicates in-use data to unused memory locations to effectively reduce average memory read latency. On average across five HPC benchmark suites, FMR provides 13% performance and 8% system-level energy improvement. | en |
dc.description.abstractgeneral | Random-access memory (RAM) or simply memory, stores the temporary data of applications that run on a computer system. Its size is determined by the worst-case application workload that the computer system is supposed to run. Through our memory utilization study of four large multi-node high-performance computing (HPC) systems, we find that memory is underutilized severely in these systems. Unused memory is a wasted resource that does nothing. In this work, we propose techniques that can make use of this wasted memory to boost computer system performance. We call these techniques Free-memory-aware Microarchitecture Techniques (FMTs). We then present an FMT for HPC systems in detail called Free-memory-aware Replication (FMR) that provides performance improvement of over 13%. | en |
dc.description.degree | M.S. | en |
dc.format.medium | ETD | en |
dc.identifier.uri | http://hdl.handle.net/10919/98745 | en |
dc.language.iso | en | en |
dc.publisher | Virginia Tech | en |
dc.rights | Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International | en |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | en |
dc.subject | Computer Architecture | en |
dc.subject | Memory | en |
dc.subject | DRAM | en |
dc.subject | HPC systems | en |
dc.title | Towards Using Free Memory to Improve Microarchitecture Performance | en |
dc.type | Thesis | en |
thesis.degree.discipline | Computer Engineering | en |
thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
thesis.degree.level | masters | en |
thesis.degree.name | M.S. | en |
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