Intra- and Inter-chip Communication Support for Asymmetric Multicore Processors with Explicitly Managed Memory Hierarchies

dc.contributor.authorRose, Benjamin Aaronen
dc.contributor.committeechairNikolopoulos, Dimitrios S.en
dc.contributor.committeememberButt, Ali R.en
dc.contributor.committeememberLowenthal, David K.en
dc.contributor.departmentComputer Scienceen
dc.date.accessioned2014-03-14T20:37:01Zen
dc.date.adate2009-06-10en
dc.date.available2014-03-14T20:37:01Zen
dc.date.issued2009-05-12en
dc.date.rdate2009-06-10en
dc.date.sdate2009-05-15en
dc.description.abstractThe use of asymmetric multi-core processors with on-chip computational accelerators is becoming common in a variety of environments ranging from scientific computing to enterprise applications. The focus of current research has been on making efficient use of individual systems, and porting applications to asymmetric processors. The use of these asymmetric processors, like the Cell processor, in a cluster setting is the inspiration for the Cell Connector framework presented in this thesis. Cell Connector adopts a streaming approach for providing data to compute nodes with high computing potential but limited memory resources. Instead of dividing very large data sets once among computation resources, Cell Connector slices, distributes, and collects work units off of a master data held by a single large memory machine. Using this methodology, Cell Connector is able to maximize the use of limited resources and produces results that are up to 63.3\% better compared to standard non-streaming approaches.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-05152009-170830en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-05152009-170830/en
dc.identifier.urihttp://hdl.handle.net/10919/32824en
dc.publisherVirginia Techen
dc.relation.haspartmain.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectCell BEen
dc.subjectmulticoreen
dc.subjectclusteren
dc.titleIntra- and Inter-chip Communication Support for Asymmetric Multicore Processors with Explicitly Managed Memory Hierarchiesen
dc.typeThesisen
thesis.degree.disciplineComputer Scienceen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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