Implementation of SCA-Resistant CPU and an ECDLP Engine on FPGA Platform

Abstract

The rapid increase in the use of embedded systems for performing secure transactions, has proportionally increased the security threat, faced by such devices. Security threats are an issue of concern at both software and hardware level. The field of cryptography has been intensively researched for secure implementation techniques, methods to attack secure systems and countermeasures to avoid such attacks. In this thesis, we provide solutions for two interesting problems in the field of hardware security using reconfigurable hardware.

First, we discuss a countermeasure to prevent side-channel analysis (SCA) attacks on an embedded system. We present an SCA-resistant processor design in the context of an embedded design flow for FPGA. It integrates an SCA-resistant custom instruction set on a soft-core CPU and derives an SCA resistance from dual-rail precharge principle. The resulting countermeasure applies to a broad class of block ciphers that consist of lookup tables and logical operations. While many countermeasures have been proposed previously, we show that our solution achieves an excellent trade-off between SCA resistance, (software and hardware) design complexity, performance, and circuit area cost.

Secondly, we present a system to attack a special type of cryptography called Elliptic Curve Cryptography(ECC). It targets the Elliptic Curve Discrete Logarithmic Problem (ECDLP) for a NIST-standardized ECC-curve over 112-bit prime field.

We implement a successful demonstration of an ECC cryptanalytic engine using the Pollard rho algorithm on a hardware-software co-integrated platform.

We propose a novel, generalized architecture for polynomial-basis multiplication over prime field and its extension to a dedicated square module. Its design strategy is portable to other prime field moduli.