Accelerating Hardware Simulation on Multi-cores

Simple item page
dc.contributor.authorNanjundappa, Maheshen
dc.contributor.committeechairShukla, Sandeep K.en
dc.contributor.committeememberHa, Dong Samen
dc.contributor.committeememberSchaumont, Patrick R.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:37:39Zen
dc.date.adate2010-06-04en
dc.date.available2014-03-14T20:37:39Zen
dc.date.issued2010-05-04en
dc.date.rdate2010-06-04en
dc.date.sdate2010-05-19en
dc.description.abstractElectronic design automation (EDA) tools play a central role in bridging the productivity gap for designing complex hardware systems. However, with an increase in the size and complexity of today's design requirements, current methodologies and EDA tools are unable to effectively mitigate the further widening of productivity gap. It is estimated that testing and verification takes 2/3rd of the total development time of complex hardware systems. Functional simulation forms the main stay of testing and verification process and is the most widely used technique for testing and verification. Most of the simulation algorithms and their implementations are designed for uniprocessor systems that cannot easily leverage the parallelism in multi-core and GPU platforms. For example, logic simulation often uses levelized sequential algorithms, whereas the discrete-event simulation frameworks for Verilog, VHDL and SystemC employ concurrency in the form of multi-threading to given an illusion of the inherent parallelism present in circuits. However, the discrete-event model of computation requires a global notion of an event-queue, which makes improving its simulation performance via parallelization even more challenging. This work investigates automatic parallelization of simulation algorithms used to simulate hardware models. In particular, we focus on parallelizing the simulation of hardware designs described at the RTL using SystemC/HDL with examples to clearly describe the parallelization. Even though multi-cores and GPUs other parallelism, efficiently exploiting this parallelism with their programming models is not straightforward. To overcome this, we also focus our research on building intelligent translators to map simulation applications onto multi-cores and GPUs such that the complexity of the low-level programming models is hidden from the designers.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-05192010-051432en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-05192010-051432/en
dc.identifier.urihttp://hdl.handle.net/10919/33002en
dc.publisherVirginia Techen
dc.relation.haspartNanjundappa_M_T_2010.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectPOSIX threadsen
dc.subjectDiscrete Event Simulation (DES)en
dc.subjectCUDAen
dc.subjectSystemC Simulationen
dc.subjectGPGPUen
dc.subjectMulti-core simulationen
dc.subjectThreading Building Blocksen
dc.titleAccelerating Hardware Simulation on Multi-coresen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

Files

Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
Nanjundappa_M_T_2010.pdf
Size:
1.41 MB
Format:
Adobe Portable Document Format
Download

Collections

Masters Theses