Functional level modeling of digital devices

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dc.contributor.authorPuthenpurayil, Venugopalen
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2019-01-31T18:27:33Zen
dc.date.available2019-01-31T18:27:33Zen
dc.date.issued1982en
dc.description.abstractFunctional level modeling techniques for modeling digital devices that vary in complexity from SSI to LSI are described in this thesis. The vehicle used for modeling is GSP, a general simulation program developed under Dr. J. R. Armstrong at Virginia Tech. These techniques have been used extensively for modeling various devices which include counters, RAMs, ROMs, microprocessor peripheral chips and CPUs. Processors modeled include the Intel 8080, the Zilog Z80 (single chip CPUs) and the Bendix BDX930 (MSI).en
dc.description.degreeMaster of Scienceen
dc.format.extentvii, 145, [1] leavesen
dc.format.mimetypeapplication/pdfen
dc.identifier.urihttp://hdl.handle.net/10919/87252en
dc.language.isoen_USen
dc.publisherVirginia Polytechnic Institute and State Universityen
dc.relation.isformatofOCLC# 9274107en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1982.P873en
dc.subject.lcshDigital computer simulationen
dc.titleFunctional level modeling of digital devicesen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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