Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAs

Abstract

In this work, we have analyzed novel p-channel nanosheet-FET (NSFET) architectures, which utilize Ge channel grown heteroepitaxially on GaAs with an intermediate AlAs etchstop/ buffer layer. The lattice matched Ge/AlAs heterostructure offers significant benefits for gate all-around (GAA) CMOS devices such as: (i) defect-free interface and channel, (ii) ease of fabrication owing to ~ 105:1 etch selectivity between AlAs and Ge, (iii) well-established and transferrable material growth and process, (iv) superior performance and low-power dissipation, (v) no limitation of sheet thickness, and (vi) higher number of vertically stacked sheets. The transition from the well-established FinFET architecture to the Ge p-NSFET will improve ION by 12% to 0.11 mA/μm, SS by 9% to 86 mV/dec and ION/IOFF ratio by ~ 5×, at the N5 node. In addition, the use of InxGa1-xAs strain template to sustain a tunable tensile strain in Ge through pseudomorphic growth, can result in an additional 40% improvement in ION and 8% in SS, at a strain of 1% for the p-NSFET. Leveraging the lattice matched Ge/AlAs growth, the 3D stacking of a large number of nanosheets is possible, and a significant boost in ION (~ 4×) is obtained with 8 layers despite of parasitics induced selfloading. In applications requiring high drive current, increasing the number of stacked Ge nanosheets is the most efficient design pathway to improve circuit delay and area-delay-product. This system shows suitability for low-power and high-performance applications for dimensions down to N0.7, where the ION is ~ 0.6mA/μm and the SS is 81 mV/dec.