A Pseudo-Binary Cascaded H-bridge Converter for Solid-State Transformer Applications and Modulation Techniques for the Minimization of the Common-Mode Voltage

The trend in power electronics converters is to be highly efficient, compact, reliable, and cost-effective. Conventionally, power converters supply or consume power from the low-voltage utility, which impacts the size and efficiency of the system. For example, the recent proliferation of electric vehicles has demanded the rapid installation of dc fast chargers (DCFC) across the country. However, most of the commercial DCFCs operate at 480 V transferring hundreds of kilowatts, resulting in large line currents which could hinder the size, cost, and efficiency of conventional DCFCs. Conversely, modular multilevel power topologies can be directly tied to the medium-voltage (MV) grid, eliminating the line-frequency transformer and the bulky line cable requirements. Among these topologies, the cascaded H-bridge (CHB) has been extensively used in the industry for MV-high-power applications because of its cost and efficiency in this operation range. Thus, it is one of the prevalent topologies for MV solid-state transformers (SSTs) The asymmetrical hybrid binary CHB (HBCHB) allows increased output voltage levels at the expense of modularity. Based on the HBCHB, a converter new modular topology regarded as the pseudo-binary CHB (PBCHB) is proposed for the ac-dc front-end stage SSTs. To operate the PBCHB, a new hybrid modulator is developed to operate the three modular structures of the PBCHB with step-like sinusoidal waveforms at near-line-frequency commutations while an asymmetrical floating capacitor (FC) module operates at high-frequency PWM commutation. The FC module does not transfer active power but serves only as a power quality enhancer of the PBCHB. However, the modular structures symmetrically transfer all the power from the MV grid to the load. With the SST structure of the PBCHB, the dc-link voltages of the H-bridges are naturally balanced; yet the proposed hybrid modulator enables equal power transfer in the three modular structures. In addition, a controller for the FC voltage is designed, analyzed, and implemented in the proposed hybrid modulator The effectiveness of the proposed front-end SST with the proposed modulation and control technique is verified in a 1.2 kV/3 kW single-phase prototype, where each module was able to transfer 1kW each. Electromagnetic interference (EMI) also impacts the cost, size, and reliability of three-phase systems because they may require bulky EMI filters to avoid self-pollution and polluting the grid. The common-mode voltage (CMV) is one important factor of EMI emissions. Thus, reducing or eliminating it could improve the cost and size of the system. Space vector pulsewidth modulation (SVWPM) can directly design the CMV output and the switching sequence of three-phase converters. However, its implementation can become complex in converters with many levels such as MV grid-tied SST converters. This dissertation uses the digital gh coordinate and proposes a set of computations to easily retrieve the converter states with a reduced CMV and generate a symmetrical switching sequence with reduced number of commutations. To do this, a single vector among the nearest three vectors (NTVs) is sufficient to implement the switching sequence for the reduced commutation and reduced CMV SVPWM. Additionally, the dc bus can be fully utilized. Unlike conventional approaches, the developed technique is easily scalable because its computational complexity does not depend on the number of levels of the converter. The proposed reduced CMV technique was verified in a three-phase 15-level 311 V/600 W unit. Moving forward in the objective of CMV reduction, a new jk-coordinate system for multilevel converters is proposed for SVPWM with eliminated CMV. With the jk coordinates, the converter states that yield zero CMV (ZCMV) can be directly computed. In addition, a single jk vector is sufficient to generate the switching sequences of NTVs. Moreover, the switching sequences feature reduced losses for high-power-factor applications in the phase that naturally commutes twice during a sampling period. Similarly, the computation burden of the ZCMV SVPWM technique presented in this dissertation is not affected by the number of levels of the converter, thus, it is scalable. The three-phase 15-level 311 V/600 W prototype was utilized to verify this technique.