A Pseudo-Binary Cascaded H-bridge Converter for Solid-State Transformer Applications and Modulation Techniques for the Minimization of the Common-Mode Voltage
| dc.contributor.author | Gutierrez Suarez, Bryan Ciro | en |
| dc.contributor.committeechair | Lai, Jih S. | en |
| dc.contributor.committeemember | Centeno, Virgilio A. | en |
| dc.contributor.committeemember | Burgos, Rolando | en |
| dc.contributor.committeemember | Southward, Steve C. | en |
| dc.contributor.committeemember | Dong, Dong | en |
| dc.contributor.department | Electrical Engineering | en |
| dc.date.accessioned | 2024-11-21T09:00:13Z | |
| dc.date.available | 2024-11-21T09:00:13Z | |
| dc.date.issued | 2024-11-20 | |
| dc.description.abstract | The trend in power electronics converters is to be highly efficient, compact, reliable, and cost-effective. Conventionally, power converters supply or consume power from the low-voltage utility, which impacts the size and efficiency of the system. For example, the recent proliferation of electric vehicles has demanded the rapid installation of dc fast chargers (DCFC) across the country. However, most of the commercial DCFCs operate at 480 V transferring hundreds of kilowatts, resulting in large line currents which could hinder the size, cost, and efficiency of conventional DCFCs. Conversely, modular multilevel power topologies can be directly tied to the medium-voltage (MV) grid, eliminating the line-frequency transformer and the bulky line cable requirements. Among these topologies, the cascaded H-bridge (CHB) has been extensively used in the industry for MV-high-power applications because of its cost and efficiency in this operation range. Thus, it is one of the prevalent topologies for MV solid-state transformers (SSTs) The asymmetrical hybrid binary CHB (HBCHB) allows increased output voltage levels at the expense of modularity. Based on the HBCHB, a converter new modular topology regarded as the pseudo-binary CHB (PBCHB) is proposed for the ac-dc front-end stage SSTs. To operate the PBCHB, a new hybrid modulator is developed to operate the three modular structures of the PBCHB with step-like sinusoidal waveforms at near-line-frequency commutations while an asymmetrical floating capacitor (FC) module operates at high-frequency PWM commutation. The FC module does not transfer active power but serves only as a power quality enhancer of the PBCHB. However, the modular structures symmetrically transfer all the power from the MV grid to the load. With the SST structure of the PBCHB, the dc-link voltages of the H-bridges are naturally balanced; yet the proposed hybrid modulator enables equal power transfer in the three modular structures. In addition, a controller for the FC voltage is designed, analyzed, and implemented in the proposed hybrid modulator The effectiveness of the proposed front-end SST with the proposed modulation and control technique is verified in a 1.2 kV/3 kW single-phase prototype, where each module was able to transfer 1kW each. Electromagnetic interference (EMI) also impacts the cost, size, and reliability of three-phase systems because they may require bulky EMI filters to avoid self-pollution and polluting the grid. The common-mode voltage (CMV) is one important factor of EMI emissions. Thus, reducing or eliminating it could improve the cost and size of the system. Space vector pulsewidth modulation (SVWPM) can directly design the CMV output and the switching sequence of three-phase converters. However, its implementation can become complex in converters with many levels such as MV grid-tied SST converters. This dissertation uses the digital gh coordinate and proposes a set of computations to easily retrieve the converter states with a reduced CMV and generate a symmetrical switching sequence with reduced number of commutations. To do this, a single vector among the nearest three vectors (NTVs) is sufficient to implement the switching sequence for the reduced commutation and reduced CMV SVPWM. Additionally, the dc bus can be fully utilized. Unlike conventional approaches, the developed technique is easily scalable because its computational complexity does not depend on the number of levels of the converter. The proposed reduced CMV technique was verified in a three-phase 15-level 311 V/600 W unit. Moving forward in the objective of CMV reduction, a new jk-coordinate system for multilevel converters is proposed for SVPWM with eliminated CMV. With the jk coordinates, the converter states that yield zero CMV (ZCMV) can be directly computed. In addition, a single jk vector is sufficient to generate the switching sequences of NTVs. Moreover, the switching sequences feature reduced losses for high-power-factor applications in the phase that naturally commutes twice during a sampling period. Similarly, the computation burden of the ZCMV SVPWM technique presented in this dissertation is not affected by the number of levels of the converter, thus, it is scalable. The three-phase 15-level 311 V/600 W prototype was utilized to verify this technique. | en |
| dc.description.abstractgeneral | The recent demands for fast chargers for electric vehicles (EV), photovoltaic (PV) energy integration, and data centers for artificial intelligence (AI) have driven the research and development of efficient, compact, and cost-effective power electronic solutions. Under these motivations, the solid-state transformer (SST) is a power electronics configuration that can benefit the EV, PV, AI, and several other applications. By eliminating the requirement of a line-frequency transformer, SSTs can be directly connected to the medium-voltage (MV) grid, reducing the weight and volume, and improving efficiency. The main reason for these advantageous attributes is the utilization of multilevel ac/dc or dc/ac converters. Among these, the cascaded H-bridge (CHB) converter has been extensively used in the industry for MV-high-power applications because of its cost, fault tolerance, and efficiency, making it a favorable converter for MV SSTs. Symmetrical modules in the CHB must commutate at the same pulsewidth modulation (PWM) when operating in an SST. An asymmetrical configuration such as the hybrid binary CHB (HBCHB) allows increased output voltage levels and low-frequency commutation at the expense of modularity. This dissertation proposes a pseudo-binary CHB (PBCHB) inspired by the HBCHB to obtain low-frequency commutations, thus, negligible switching losses in the SST. The PBCHB has symmetrical modules that transfer balanced active power with negligible switching losses while an asymmetrically smaller module enhances the power quality with PWM operation. To do this, a new hybrid modulator and controller were designed, analyzed, and verified in this dissertation. The effectiveness of the proposed front-end PBCHB-based SST with the developed modulation and control techniques is verified in an MV 1.2 kV/3 kW single-phase prototype. Electromagnetic interference (EMI) filters can impact the cost, size, and reliability of SSTs. The common-mode voltage (CMV) that power converters generate is one type of EMI emissions that could impact the cost and size of the system. The modulation technique called space vector pulsewidth modulation (SVWPM) has the freedom to design a switching sequence able to reduce or eliminate the CMV. However, implementing the SVPWM can become complex in MV grid-tied SST converters (PBCHB, CHB, HBCHB) with many voltage levels. This dissertation uses the digital gh coordinate system and a new jk coordinate system to reduce and eliminate the CMV, respectively. These coordinates systems have the advantage of reduced computational complexity in multilevel converters with large number of output voltage levels increases. The proposed techniques can retrieve back the abc signals for the PWM drivers without repetitive iterations. Moreover, the proposed techniques can generate symmetrical switching sequences with reduced number of commutations and switching losses in the converter. To do this, the computation of a single vector among the nearest three vectors is sufficient to implement the switching sequences of SVPWM. As a result, the computational complexity of the SVPWM techniques in this dissertation is constant and does not vary with the number of output voltage levels, making them easily scalable solutions compared to previous solutions in the literature. The proposed reduced and eliminated CMV SVPWM techniques were verified in a three-phase 15-level 311 V/600 W HBCHB unit in inverting mode. | en |
| dc.description.degree | Doctor of Philosophy | en |
| dc.format.medium | ETD | en |
| dc.identifier.other | vt_gsexam:41759 | en |
| dc.identifier.uri | https://hdl.handle.net/10919/123638 | |
| dc.language.iso | en | en |
| dc.publisher | Virginia Tech | en |
| dc.rights | In Copyright | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject | Asymmetrical Multilevel Converter | en |
| dc.subject | Common-Mode Voltage | en |
| dc.subject | Coordinate Transformation | en |
| dc.subject | DC Voltage Balancing | en |
| dc.subject | Hybrid Modulator | en |
| dc.subject | Medium Voltage | en |
| dc.subject | Solid-State Transformer | en |
| dc.subject | Space Vector Pulsewidth Modulation | en |
| dc.title | A Pseudo-Binary Cascaded H-bridge Converter for Solid-State Transformer Applications and Modulation Techniques for the Minimization of the Common-Mode Voltage | en |
| dc.type | Dissertation | en |
| thesis.degree.discipline | Electrical Engineering | en |
| thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
| thesis.degree.level | doctoral | en |
| thesis.degree.name | Doctor of Philosophy | en |