Scalable and Reconfigurable True-Time Delay Line for Integrated Radio-Frequency Recurrent Neural Processors

Abstract

This paper presents a scalable and tunable delay-line architecture for analog recurrent neural networks (RNNs) operating directly in the RF-domain. Previous research has shown the RF-domain RNNs are capable of performing real-time anomaly detection in wireless systems while reducing the inference latency of the wireless system to be one RF clock cycle. The original RF-domain RNN structure relies on a passive tapped transmission line delay for sequential input samples, limiting the architecture's scalability, power efficiency, and frequency adaptability. Transmission lines have too much attenuation, become impractically large for chip integration, and are untunable. To eliminate these limitations, the passive transmission line delay is replaced with an active delay line made up of cascaded gm-C all-pass filter (APF) cells. The APF cells achieve true-time delay while maintaining low attenuation, low power consumption, high linearity, and have reconfigurable delay characteristics. The proposed solution utilizes compact integration, signal preservation along the delay line, and dynamic tuning for different carrier frequencies or true-time delay needs. A full model of the active delay line and it's integration with the RF-RNN architecture is developed in GlobalFoundaries 65-nm BiCMOS technology. The model includes delay characterization, analysis of loading effects, and noise analysis. The simulation results show that the gm-C APF delay network enables scalable RF-RNN implementations while maintaining anomaly classification performance accuracy under realistic timing variations. This work demonstrates a key step towards practical RF-domain neural processors capable of supporting real-time wireless systems for 5G and beyond.