Behavioral delay fault modeling and test generation

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dc.contributor.authorJoshi, Anand Mukunden
dc.contributor.committeechairArmstrong, James R.en
dc.contributor.committeememberCyre, Walling R.en
dc.contributor.committeememberGray, Festus Gailen
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:41:36Zen
dc.date.adate2009-07-29en
dc.date.available2014-03-14T21:41:36Zen
dc.date.issued1994-05-05en
dc.date.rdate2009-07-29en
dc.date.sdate2009-07-29en
dc.description.abstractAs the speed of operation of VLSI devices has increased, delay fault testing has become a more important factor in VLSI testing. Due to the large number of gates in a VLSI circuit, the gate level test generation methodologies may become infeasible for delay test generation. In this work, a new behavioral delay fault model that aims at simplifying the delay test generation problem for digital circuits is presented. The model is defined using VHDL. It is shown that each defined behavioral level delay fault can be mapped to a gate level equivalent fault and/or physical failure. A systematic way of representing a behavioral model in terms of a data flow graph is presented. A behavioral level input-output path is defined and a strategy to generate tests for delay faults along a behavioral path is presented. It is then shown that tests developed from the behavioral model can test a gate level equivalent circuit for path delay faults.en
dc.description.degreeMaster of Scienceen
dc.format.extentx, 170 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-07292009-090436en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-07292009-090436/en
dc.identifier.urihttp://hdl.handle.net/10919/43996en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1994.J674.pdfen
dc.relation.isformatofOCLC# 31047624en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1994.J674en
dc.subject.lcshFault-tolerant computingen
dc.subject.lcshIntegrated circuits -- Very large scale integration -- Testingen
dc.subject.lcshVHDL (Computer hardware description language)en
dc.titleBehavioral delay fault modeling and test generationen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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