A framework for synthesis from VHDL

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dc.contributor.authorShah, Sandeep R.en
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:30:27Zen
dc.date.adate2010-03-02en
dc.date.available2014-03-14T21:30:27Zen
dc.date.issued1991en
dc.date.rdate2010-03-02en
dc.date.sdate2010-03-02en
dc.description.abstractThis thesis describes the design and implementation of a hardware synthesis system based on design descriptions provided in VHDL. Several aspects of the synthesis problem are examined. These include the design of an internal format to represent multiple levels of design information, algorithms for synthesis, optimizations, and verification of the synthesis process. Key features of this system include the ability to synthesize models that span a wide range of design description abstraction levels. The synthesis system internal format contains data structures for algorithmic, dataflow, as well as structural VHDL constructs. This framework for performing synthesis over a wide range of abstraction levels is the novel feature of this system. Optimizations for register-transfer level (dataflow) models are discussed along with their implementation. The design and implementation of the synthesis library, which contains information about the hardware components available to perform the synthesis, is also discussed. The output of the synthesis system is in the form of two files, an RNL format netlist and a purely structural VHDL netlist. In order to produce the actual hardware layout, the RNL netlist must be input to VPNR, a standard cell place and route system. The structural VHDL may be simulated to verify the synthesis process. Results of mixed level synthesis are provided.en
dc.description.degreeMaster of Scienceen
dc.format.extent98 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-03022010-020143en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-03022010-020143/en
dc.identifier.urihttp://hdl.handle.net/10919/41322en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1991.S523.pdfen
dc.relation.isformatofOCLC# 25404391en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1991.S523en
dc.subject.lcshVHDL (Computer hardware description language)en
dc.titleA framework for synthesis from VHDLen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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