Logical Representation of FPGAs and FPGA Circuits within the SCA

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dc.contributor.authorCarrick, Matthewen
dc.contributor.committeechairDietrich, Carl B.en
dc.contributor.committeememberAthanas, Peter M.en
dc.contributor.committeememberReed, Jeffrey H.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:40:58Zen
dc.date.adate2009-08-04en
dc.date.available2014-03-14T20:40:58Zen
dc.date.issued2009-07-02en
dc.date.rdate2009-08-04en
dc.date.sdate2009-07-01en
dc.description.abstractA very basic engineering tradeoff is performance versus flexibility and this design choice must be made when developing a software radio. Hardware devices such as General Purpose Processors (GPPs), Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) all provide a designer with choices along the performance versus flexibility spectrum. The designer must choose a combination of GPP, DSP, FPGA and ASIC devices to balance the needs of performance versus flexibility. The Software Communications Architecture (SCA) is a specification for a software radio architecture produced by the Joint Program Executive Office (JPEO) Joint Tactical Radio System (JTRS). The 2.2 revision of the SCA only implies support for GPPs, with no specified support for additional devices such as FPGAs. However, FPGA integration within the scope of the SCA is still possible. The integration of an additional processing hardware device other than a GPP requires the ability to logically represent the device within the Core Framework. This representation is implemented within the OSSIE Core Framework, an open source implementation of the SCA. The representation requires the support of multiple implementations of signal processing components within the framework, a simple component deployment model, and the abstraction of the FPGA interactions into a software component.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-07012009-203400en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-07012009-203400/en
dc.identifier.urihttp://hdl.handle.net/10919/33858en
dc.publisherVirginia Techen
dc.relation.haspartMatt_Carrick_Thesis.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectField programmable gate arraysen
dc.subjectSoftware Radioen
dc.subjectSCAen
dc.subjectOSSIEen
dc.titleLogical Representation of FPGAs and FPGA Circuits within the SCAen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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