High-Level CSP Model Compiler for FPGAs

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dc.contributor.authorAsthana, Rohit Mohanen
dc.contributor.committeechairAthanas, Peter M.en
dc.contributor.committeememberSchaumont, Patrick R.en
dc.contributor.committeememberPlassmann, Paul E.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:50:44Zen
dc.date.adate2011-01-19en
dc.date.available2014-03-14T20:50:44Zen
dc.date.issued2010-12-14en
dc.date.rdate2011-01-19en
dc.date.sdate2010-12-23en
dc.description.abstractThe ever-growing competition in current electronics industry has resulted in stringent time-to-market goals and reduced design time available to engineers. Lesser design time has subsequently raised a need for high-level synthesis design methodologies that raise the design to a higher level of abstraction. Higher level of abstraction helps in increasing the predictability and productivity of the design and reduce the number of bugs due to human-error. It also enables the designer to try out dierent optimization strategies early in the design stage. In-spite of all these advantages, high-level synthesis design methodologies have not gained much popularity in the mainstream design flow mainly because of the reasons like lack of readability and reliability of the generated register transfer level (RTL) code. The compiler framework presented in this thesis allows the user to draw high-level graphical models of the system. The compiler translates these models into synthesizeable RTL Verilog designs that exhibit their desired functionality following communicating sequential processes (CSP) model of computation. CSP model of computation introduces a good handshaking mechanism between different components in the design that makes designs less prone to timing violations during implementation and bottlenecks while in actual operation.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-12232010-123433en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-12232010-123433/en
dc.identifier.urihttp://hdl.handle.net/10919/36428en
dc.publisherVirginia Techen
dc.relation.haspartAsthana_RM_T_2010.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectHigh-Level Synthesisen
dc.subjectFPGAsen
dc.subjectModels of Computation (MoC)en
dc.subjectCommunicating Sequential Processes (CSP)en
dc.subjectAutocode Generationen
dc.titleHigh-Level CSP Model Compiler for FPGAsen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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