Simulation of large-scale system-level models

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Virginia Tech


In this thesis, the efficient simulation of large-scale system-level VHDL models is analyzed. The system-level models chosen for the investigation are multicomputer networks, which are scalable up to thousands of processing nodes. Initially, a classification of parallel processing architectures is presented along with performance criteria and design issues related to the various interconnection network topologies. Communication and synchronization issues of MIMD systems are explored. A major limitation of planar tree structures is discussed along with a solution to help alleviate the problem, which is to make use of the binary fat-tree. Practical aspects of efficiently simulating large behavioral and structural models (using the fat-tree model as a case study), on a uniprocessor system are analyzed. The system resources of the workstation used to perform the simulations are carefully monitored to see where resource utilization problems usually occur. The size of the model is increased and the run time of the simulation compared with that of smaller sized models. A memory threshold level is detected after which memory resource contention problems occur and the simulation efficiency declines.

One of the problems observed in simulating complex models is the fact that simulation runs take a very long time to execute. A multicomputer using the fat-tree interconnection network is proposed as a suitable architecture for the distributed simulation of VHDL models. Various algorithms used for the parallel discrete event simulation (PDES) of VHDL models are evaluated. The feasibility of this approach is evaluated by analyzing the factors affecting the performance of the proposed architecture. The number of hops a message takes to travel from one processor to another in the fat-tree is used to estimate the time of an event message between two processors. The roll-back and communication costs amongst the processing nodes are taken into consideration when evaluating the speedup of the simulation time of a VHDL model, simulated over multiple processors. The speedup of the simulation obtained by using the fat-tree topology is compared with the results obtained with a linear array of processors. The future inclusion of the "shared variable" into the language and its impact on the implementation of parallel simulators on multicomputer networks is analyzed.