Parallel processor architecture for a digital beacon receiver

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dc.contributor.authorRunyon, Ginger R.en
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:30:58Zen
dc.date.adate2009-03-04en
dc.date.available2014-03-14T21:30:58Zen
dc.date.issued1990en
dc.date.rdate2009-03-04en
dc.date.sdate2009-03-04en
dc.description.abstractA digital beacon receiver has been developed to monitor the OLYMPUS satellite beacons. The receiver accepts a nominal 10 MHz IF input and processes the signal using digital signal processing techniques. Fast Fourier transforms are used to locate the carrier within 0.5 Hz. The outputs of the receiver include the frequency and the power of the carrier.en
dc.description.degreeMaster of Scienceen
dc.format.extentix, 115 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-03042009-040951en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-03042009-040951/en
dc.identifier.urihttp://hdl.handle.net/10919/41422en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1990.R869.pdfen
dc.relation.haspartLD5655.V855_1990.R869_drw01a.pdfen
dc.relation.haspartLD5655.V855_1990.R869_drw01b.pdfen
dc.relation.isformatofOCLC# 22607030en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1990.R869en
dc.subject.lcshEarth stations (Satellite telecommunication) -- Researchen
dc.subject.lcshParallel processing (Electronic computers) -- Designen
dc.subject.lcshSignal processing -- Digital techniquesen
dc.titleParallel processor architecture for a digital beacon receiveren
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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