Communication Synthesis for MIMO Decoder Matrices

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dc.contributor.authorQuesenberry, Joshua Danielen
dc.contributor.committeechairPatterson, Cameron D.en
dc.contributor.committeememberHsiao, Michael S.en
dc.contributor.committeememberMartin, Thomas L.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-12-18T21:00:22Zen
dc.date.adate2011-09-15en
dc.date.available2014-12-18T21:00:22Zen
dc.date.issued2011-08-09en
dc.date.rdate2014-12-16en
dc.date.sdate2011-08-17en
dc.description.abstractThe design in this work provides an easy and cost-efficient way of performing an FPGA implementation of a specific algorithm through use of a custom hardware design language and communication synthesis. The framework is designed to optimize performance with matrix-type mathematical operations. The largest matrices used in this process are 4x4 matrices. The primary example modeled in this work is MIMO decoding. Making this possible are 16 functional unit containers within the framework, with generalized interfaces, which can hold custom user hardware and IP cores. This framework, which is controlled by a microsequencer, is centered on a matrix-based memory structure comprised of 64 individual dual-ported memory blocks. The microsequencer uses an instruction word that can control every element of the architecture during a single clock cycle. Routing to and from the memory structure uses an optimized form of a crossbar switch with predefined routing paths supporting any combination of input/output pairs needed by the algorithm. A goal at the start of the design was to achieve a clock speed of over 100 MHz; a clock speed of 183 MHz has been achieved. This design is capable of performing a 4x4 matrix inversion within 335 clock cycles, or 1,829 ns. The power efficiency of the design is measured at 17.15 MFLOPS/W.en
dc.description.degreeMaster of Scienceen
dc.format.mediumETDen
dc.identifier.otheretd-08172011-195854en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-08172011-195854/en
dc.identifier.urihttp://hdl.handle.net/10919/51149en
dc.publisherVirginia Techen
dc.relation.haspartQuesenberry_JD_T_20911.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectCommunication Synthesisen
dc.subjectMIMOen
dc.subjectField programmable gate arraysen
dc.subjectXilinxen
dc.titleCommunication Synthesis for MIMO Decoder Matricesen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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