Methodology for structured VHDL model development

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dc.contributor.authorGummadi, Ramen
dc.contributor.committeechairGray, Festus Gailen
dc.contributor.committeememberArmstrong, James R.en
dc.contributor.committeememberReed, Jeffrey H.en
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:32:08Zen
dc.date.adate2010-03-17en
dc.date.available2014-03-14T21:32:08Zen
dc.date.issued1995-04-05en
dc.date.rdate2010-03-17en
dc.date.sdate2010-03-17en
dc.description.abstractThe Rapid Prototyping of Application Specific Signal Processors (RASSP) program seeks an improvement in the time required to take a design from concept to fielded prototype or to upgrade an existing design, with similar improvements in design quality and life cycle cost. The term Rapid System Prototyping signifies the need to develop systems in significantly less time or with significantly less effort, and thus provides a solution to the main problem facing the design community. Entire systems are synthesized from models in hardware description languages (HDLs). The goal of this thesis is to provide a methodology for rapidly creating a database, that can be reused thus decreasing design cost and time for both current and future projects. To demonstrate the methodology, this thesis describes the development of VHDL primitives supporting digital signal processing (DSP) and image processing operations for two of the RASSP specific applications: 1) Synthetic aperture radar image processor (SAR) and 2) Automatic target recognition (ATR) image processing algorithm. Different techniques are investigated to populate these VHDL libraries using commercial tools. The thesis proposes techniques for solving some problems related to the use of commercial tools to generate VHDL code. It includes a full implementation of the SAR processor algorithm developed from DSP primitives.en
dc.description.degreeMaster of Scienceen
dc.format.extentviii, 110 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-03172010-020739en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-03172010-020739/en
dc.identifier.urihttp://hdl.handle.net/10919/41730en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1995.G866.pdfen
dc.relation.isformatofOCLC# 34783748en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectdesign qualityen
dc.subjectproductivityen
dc.subject.lccLD5655.V855 1995.G866en
dc.titleMethodology for structured VHDL model developmenten
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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