Methodology for VHDL performance model construction and validation

dc.contributor.authorVuppala, Srilekhaen
dc.contributor.committeechairGray, Festus Gailen
dc.contributor.committeememberArmstrong, James R.en
dc.contributor.committeememberCyre, W. R.en
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:44:00Zen
dc.date.adate2008-08-29en
dc.date.available2014-03-14T21:44:00Zen
dc.date.issued1996en
dc.date.rdate2008-08-29en
dc.date.sdate2008-08-29en
dc.description.abstractHardware description languages(HDLs) are frequently used to construct performance models to represent systems early in the design process. This research study has resulted in the development of a methodology to construct VHDL performance models which will help to significantly reduce the time from an initial conception to a working design. To further reduce development time, reuse of existing structural primitives is emphasized. Typical models of multi-processor architectures are very large and complex. Validation of theses models is difficult and time consuming. This thesis also develops a methodology for model validation. A seventeen processor raceway architecture, that was developed as a part of the ongoing RASSP(Rapid Prototyping of Application Specific Signal Processors) project, is used as a template to illustrate the new methodologies of performance model construction and model validation. The design consists of seventeen processors interconnected by multiple crossbar switches. Two software algorithms were mapped onto the architecture: a Synthetic Aperture Radar(SAR) Range Processing Algorithm and a SAR Multiswath Processing Algorithm. The methodologies developed in this thesis will considerably reduce the amount of time needed to construct and validate performance models of complex multi-processor architectures.en
dc.description.degreeMaster of Scienceen
dc.format.extentxi, 120 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-08292008-063326en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-08292008-063326/en
dc.identifier.urihttp://hdl.handle.net/10919/44488en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1996.V877.pdfen
dc.relation.isformatofOCLC# 35217170en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectVHDLen
dc.subjectperformance modelingen
dc.subjectmodel constructionen
dc.subjectmodel validationen
dc.subject.lccLD5655.V855 1996.V877en
dc.titleMethodology for VHDL performance model construction and validationen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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