Assembly Yield Model for Area Array Packages
| dc.contributor.author | Sharma, Sanjay | en |
| dc.contributor.committeechair | Sarin, Subhash C. | en |
| dc.contributor.committeemember | Borgesen, Peter | en |
| dc.contributor.committeemember | Sturges, Robert H. | en |
| dc.contributor.department | Industrial and Systems Engineering | en |
| dc.date.accessioned | 2014-03-14T20:32:49Z | en |
| dc.date.adate | 2000-04-05 | en |
| dc.date.available | 2014-03-14T20:32:49Z | en |
| dc.date.issued | 2000-03-06 | en |
| dc.date.rdate | 2004-04-05 | en |
| dc.date.sdate | 2000-03-24 | en |
| dc.description.abstract | The traditional design of printed circuit board assembly focuses on finding a set of parameter values (that characterizes the process), such that the desired circuit performance specifications are met. It is usually assumed that this set of values can be accurately realized when the circuit or the assembly is built. Unfortunately, this assumption is not realistic for assemblies produced in mass scale. Fluctuations in manufacturing processes cause defects in actual values of the parameters. This variability in design parameters, in turn, causes defects in the functionality of the assemblies. The ratio of the acceptable assemblies to total assemblies produced constitutes the yield of the assembly process. Assembly yields of area array packages are heavily dependent on design of the board as much as package and process parameters. The economics of IC technology is such that the maximization of yield rather than the optimization of performance has become the topic of prime importance. The projected value of yield has always been a factor for consideration in the advancement of Integrated Chip technology. Due to considerable reduction in the package size, minimum allowable tolerance and tight parameter variations, electronic assemblies have to be simulated, characterized and tested before translating them to a production facility. Also, since the defect levels are measured in parts per million, it is impractical to build millions of assemblies for the purpose of identifying the best parameter. A mathematical model that relates design parameters and their variability to assembly yield can help in the effective estimation of the yield. This research work led to the development of a mathematical model that can incorporate variability in the package, board and assembly related parameters and construction of an effective methodology to predict the assembly yield of area array packages. The assembly yield predictions of the model are based on the characteristics of input variables (whether they follow a normal, empirical or experimental distribution). By incorporating the tail portion of the parameter distribution (up to ±6 standard deviation on normal distribution), a higher level of accuracy in assembly yield prediction is achieved. An estimation of the interaction of parameters is obtained in terms of the expected number of defective joints and/or components and a degree of variability around this expected value. As an implementation of the mathematical model, a computer program is developed. The software is user friendly and prompts the user for information on the input variables, it predicts the yield as expected number of defective joints per million and expected number of defective components (assemblies) per million. The software can also be used to predict the number of defects for a user-specified number of components (less or more than one million assemblies). The area array assembly yield model can be used to determine the impact of process parameter variations on assembly yields. The model can also be used to assess the manufacturability of a new design, represent the capability of an assembly line for bench marking purposes, help modify designs for better yield, and to define the minimum acceptable manufacturability standards and tolerances for components, boards and designs. | en |
| dc.description.degree | Master of Science | en |
| dc.identifier.other | etd-03242000-10030026 | en |
| dc.identifier.sourceurl | http://scholar.lib.vt.edu/theses/available/etd-03242000-10030026/ | en |
| dc.identifier.uri | http://hdl.handle.net/10919/31532 | en |
| dc.publisher | Virginia Tech | en |
| dc.relation.haspart | Thesis.PDF | en |
| dc.rights | In Copyright | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject | CSP | en |
| dc.subject | Yield | en |
| dc.subject | Joints | en |
| dc.subject | Defects | en |
| dc.subject | BGA | en |
| dc.subject | Open | en |
| dc.subject | DCA | en |
| dc.title | Assembly Yield Model for Area Array Packages | en |
| dc.type | Thesis | en |
| thesis.degree.discipline | Industrial and Systems Engineering | en |
| thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
| thesis.degree.level | masters | en |
| thesis.degree.name | Master of Science | en |
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