JHDLBits: An Open-Source Model for FPGA Design Automation

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dc.contributor.authorPoetter, Alexandra Vanessaen
dc.contributor.committeechairAthanas, Peter M.en
dc.contributor.committeememberMartin, Thomas L.en
dc.contributor.committeememberPatterson, Cameron D.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2011-08-06T16:06:25Zen
dc.date.adate2004-09-22en
dc.date.available2011-08-06T16:06:25Zen
dc.date.issued2004-07-19en
dc.date.rdate2004-09-22en
dc.date.sdate2004-08-25en
dc.description.abstractToday's Field Programmable Gate Array (FPGA) research community could use an extensible tool flow enabling designers to examine new algorithms and new methods of interacting with FPGA configurations. One such flow is JHDLBits, which integrates two prominent FPGA design environments: JHDL and JBits. JHDLBits offers the low-level access and control provided by JBits with the high-level structural circuit design of JHDL. Furthermore, the JHDLBits flow provides greater control of resource manipulation, placement, and routing, and gives researchers a sandbox to explore advanced interactions with FPGA configurations. This thesis presents the overall architecture of the open-source JHDLBits project. Details are provided on how the core components -- JHDL, JBits3 for Virtex-II, the ADB connectivity database, and VTsim, a Virtex-II device simulator -- are linked together to provide an integrated design environment. Strategies and philosophies of the open source movement are also examined to successfully establish the support for and involvement of the FPGA research community throughout the JHDLBits open source endeavor.en
dc.description.degreeMaster of Scienceen
dc.format.mediumETDen
dc.identifier.otheretd-08252004-140501en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-08252004-140501en
dc.identifier.urihttp://hdl.handle.net/10919/10121en
dc.publisherVirginia Techen
dc.relation.haspartapoetter_thesis.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectHardware Description Languageen
dc.subjectJHDLBitsen
dc.subjectJHDLen
dc.subjectJBitsen
dc.subjectField programmable gate arraysen
dc.subjectDesign Automationen
dc.titleJHDLBits: An Open-Source Model for FPGA Design Automationen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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