Implementation of a 2-D fast Fourier transform on an FPGA-based computing platform

dc.contributor.authorShirazi, Nabeelen
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:47:04Zen
dc.date.adate2005-10-07en
dc.date.available2014-03-14T21:47:04Zen
dc.date.issued1995en
dc.date.rdate2005-10-07en
dc.date.sdate2005-10-07en
dc.description.abstractThe two dimensional fast Fourier transform (FFT) is a useful operation in many digital signal processing applications, but it is often avoided due to its large computational requirements. This thesis presents the implementation and performance figures for the fast Fourier transform on an FPGA-based custom computer. The computation of a 2-D FFT requires O(N²log₂N ) complex floating point arithmetic operations for an NxN image. By implementing the FFT algorithm on a custom computing machine (CCM) called Splash-2, a computation speed of at least 180 Mflops and a speed-up of 23 times over a SPARC-10 workstation is achieved.en
dc.description.degreeMaster of Scienceen
dc.format.extentix, 75 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-10072005-094832en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-10072005-094832/en
dc.identifier.urihttp://hdl.handle.net/10919/45066en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1995.S448.pdfen
dc.relation.isformatofOCLC# 34424820en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1995.S448en
dc.titleImplementation of a 2-D fast Fourier transform on an FPGA-based computing platformen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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