Using High-level Synthesis to Predict and Preempt Attacks on Industrial Control Systems
| dc.contributor.author | Franklin, Zane Ryan | en |
| dc.contributor.committeechair | Patterson, Cameron D. | en |
| dc.contributor.committeemember | Baumann, William T. | en |
| dc.contributor.committeemember | Schaumont, Patrick R. | en |
| dc.contributor.department | Electrical and Computer Engineering | en |
| dc.date.accessioned | 2014-04-22T08:00:22Z | en |
| dc.date.available | 2014-04-22T08:00:22Z | en |
| dc.date.issued | 2014-04-21 | en |
| dc.description.abstract | As the rate and severity of malicious software attacks have escalated, industrial control systems (ICSes) have emerged as a particularly vulnerable target. ICSes govern the automation of the physical processes in industries such as power, water, oil and manufacturing. In contrast to the personal computing space, where attackers attempt to capture information or computing resources, the attacks directed at ICSes aim to degrade or destroy the physical processes or plants maintained by the ICS. Exploits with potentially catastrophic results are sold on brokerages to any interested party. Previous efforts in ICS security implicitly and mistakenly trust internal software. This thesis presents an architecture for trust enhancement of critical embedded processes (TECEP). TECEP assumes that all software can be or has already been compromised. Trust is instead placed in hardware that is invisible to any malicious software. Software processes critical for stable operation are duplicated in hardware, along with a supervisory process to monitor the behavior of the plant. Furthermore, a copy of the software and a model of the plant are implemented in hardware in order to estimate the system's future behavior. In the event of an attack, the hardware can successfully identify the plant's abnormal behavior in either the present or the future and supersede the software's directives, allowing the plant to continue functioning correctly. This approach to ICS security can be retrofitted to existing ICSes, has minimal impact on the ICS design process, and modestly increases hardware requirements in a programmable system-on-chip. | en |
| dc.description.degree | Master of Science | en |
| dc.format.medium | ETD | en |
| dc.identifier.other | vt_gsexam:2788 | en |
| dc.identifier.uri | http://hdl.handle.net/10919/47491 | en |
| dc.publisher | Virginia Tech | en |
| dc.rights | In Copyright | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject | Industrial control systems | en |
| dc.subject | security | en |
| dc.subject | reconfigurable platform | en |
| dc.subject | high-level synthesis | en |
| dc.subject | system-on-chip | en |
| dc.title | Using High-level Synthesis to Predict and Preempt Attacks on Industrial Control Systems | en |
| dc.type | Thesis | en |
| thesis.degree.discipline | Computer Engineering | en |
| thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
| thesis.degree.level | masters | en |
| thesis.degree.name | Master of Science | en |