Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating
| dc.contributor.author | Kindel, David Garret | en |
| dc.contributor.committeechair | Nazhandali, Leyla | en |
| dc.contributor.committeemember | Feng, Wu-chun | en |
| dc.contributor.committeemember | Hsiao, Michael S. | en |
| dc.contributor.department | Electrical and Computer Engineering | en |
| dc.date.accessioned | 2016-09-02T08:00:51Z | en |
| dc.date.available | 2016-09-02T08:00:51Z | en |
| dc.date.issued | 2016-09-01 | en |
| dc.description.abstract | Modern devices such as smartphones and smartwatches spend a large amount of their life idle, waiting for external events. During this time, they are expending energy, using up battery life. Increasing power consumption is a rising concern to users and researchers alike. Power gating, turning off a blocks of hardware when idle, reduces static power consumption. The Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) currently employed in processors leak current. Even in power gated circuits, MOSFET power gating may only save between 60-80% of power. A different type of switch, a Nanoelectromechanical Systems (NEMS) switch, presents an air gap between the source and drain while in the off state, eliminating subthreshold leakage current. The NEMS switch is slower to operate and only has a finite number of switching before breaking. They should be switched with caution. Proposed in this thesis is a hybrid power gating model wherein a MOSFET is placed in series with a NEMS switch. Power gating the Floating Point Unit (FPU) of a processor is studied through the use of modern open source computer architecture simulators. Each switch type is used to model power gating to observe energy savings and performance costs. The hybrid power gating model is more flexible across a variety of applications. Energy savings are comparable to single NEMS switch power gating for applications with low FPU activity. Any performance loss remains low, matching that of MOSFETs. Processor electrical costs are heavily reduced while devices remain operating at a near-optimal speed. | en |
| dc.description.degree | Master of Science | en |
| dc.format.medium | ETD | en |
| dc.identifier.other | vt_gsexam:7944 | en |
| dc.identifier.uri | http://hdl.handle.net/10919/72871 | en |
| dc.publisher | Virginia Tech | en |
| dc.rights | In Copyright | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject | NEMS | en |
| dc.subject | Power Gating | en |
| dc.subject | Low Power | en |
| dc.subject | Simulator | en |
| dc.subject | Computer Architecture | en |
| dc.title | Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating | en |
| dc.type | Thesis | en |
| thesis.degree.discipline | Computer Engineering | en |
| thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
| thesis.degree.level | masters | en |
| thesis.degree.name | Master of Science | en |
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