Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity

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dc.contributor.authorRaja Gopalan, Sureshwaren
dc.contributor.committeechairPatterson, Cameron D.en
dc.contributor.committeememberMartin, Thomas L.en
dc.contributor.committeememberPlassmann, Paul E.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:45:05Zen
dc.date.adate2010-09-24en
dc.date.available2014-03-14T20:45:05Zen
dc.date.issued2010-09-01en
dc.date.rdate2012-04-12en
dc.date.sdate2010-09-09en
dc.description.abstractFPGA implementation tool speed has not kept pace with the increase in design size and FPGA density. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We address the implementation problem using a divide-and-conquer approach. The PATIS automatic floorplanner enables dynamic modular design, which sacrifices some design speed and area optimization for faster implementation of layout changes, including addition of debug logic. Automatic generation of a timing-driven floorplan for a partially reconfigurable design aims to remove the need for implementation iterations to meet all constraints. Floorplan speculation may anticipate small changes to a design. Although PATIS supports incremental design, complete re-implementation is still rapid because the partial bitstream for each block is generated by independent concurrent invocations of the standard Xilinx tools.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-09092010-094913en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-09092010-094913/en
dc.identifier.urihttp://hdl.handle.net/10919/34993en
dc.publisherVirginia Techen
dc.relation.haspartRajaGopalan_T_2010.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectFPGAsen
dc.subjectReconfigurable Computingen
dc.subjectAutomatic Floorplanningen
dc.titleTiming-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivityen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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