Micro-operation perturbations in chip level fault modeling

dc.contributor.authorChao, Chien-Hungen
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2017-11-09T20:41:39Zen
dc.date.available2017-11-09T20:41:39Zen
dc.date.issued1988en
dc.description.abstractIn chip level testing using hardware description language approach, a difficult question to answer is: What is the best micro-operation perturbation for modeling fault at the chip level? In this thesis, an automatic evaluation system is developed to determine the best micro-operation perturbation. The measure used is the gate level stuck-at fault coverage achieved by the tests derived to cover the micro-operation perturbation faults. For small combinational circuits, it is shown that perturbing the elements into the logic dual is a good choice. For large combinational circuits, it is shown that there is very little variation in the gate level coverage achieved by the various microoperation faults. In this case, if coverage is to be improved, the micro-operation perturbation method must be augmented by other techniques.en
dc.description.degreeMaster of Scienceen
dc.format.extentx, 129 leavesen
dc.format.mimetypeapplication/pdfen
dc.identifier.urihttp://hdl.handle.net/10919/80061en
dc.language.isoen_USen
dc.publisherVirginia Polytechnic Institute and State Universityen
dc.relation.isformatofOCLC# 18115954en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1988.C554en
dc.subject.lcshPerturbation (Quantum dynamics)en
dc.subject.lcshElectric fault locationen
dc.titleMicro-operation perturbations in chip level fault modelingen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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